[DONE] CFGR in STM32F4xx/hal_lld.c and maybe other STM32
Posted: Thu Sep 12, 2013 7:05 pm
Hi,
Looking at os/hal/platforms/STM32F4xx/hal_lld.c, around line 209:
I'm wondering why ORing is used here. It relies on CFGR being 0 initially which is not the case e.g. when using a bootloader and jumping into app code or similar.
Replacing "|=" with "=" at this position seems to have no negative effect.
Also, other settings (PLLI2SCFGR,...) are assigned as well and not OR'ed.
If there was a certain reason for ORin and not assignment (glich prevention anywhere?) then it might be good idea to mention that explicitly in the code.
Looking at os/hal/platforms/STM32F4xx/hal_lld.c, around line 209:
Code: Select all
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
I'm wondering why ORing is used here. It relies on CFGR being 0 initially which is not the case e.g. when using a bootloader and jumping into app code or similar.
Replacing "|=" with "=" at this position seems to have no negative effect.
Also, other settings (PLLI2SCFGR,...) are assigned as well and not OR'ed.
If there was a certain reason for ORin and not assignment (glich prevention anywhere?) then it might be good idea to mention that explicitly in the code.