ChibiOS Free Embedded RTOS

We have used this timer patch to add timer 15, 16, 17, 19 support to the stm32f37x.

Your feed back is appreciated.

How do I attach a patch file? I am getting The extension " " is not allowed for everything I have tried.

From eeff56419863448964e4dececd8aee6a408ab3eb Mon Sep 17 00:00:00 2001
From: Timothy Webster <[email protected]>
Date: Sun, 1 Dec 2013 23:31:44 -0500
Subject: [PATCH] Timer 15, 16, 17, 19

Add additional timers supported by stm32f3xx
---
os/hal/platforms/STM32/TIMv1/icu_lld.c | 117 ++++++++++++++++++++++++++++++++
os/hal/platforms/STM32/TIMv1/icu_lld.h | 118 ++++++++++++++++++++++++++++++++-
os/hal/platforms/STM32F37x/stm32_isr.h | 8 +++
os/hal/platforms/STM32F37x/stm32_rcc.h | 102 ++++++++++++++++++++++++++++
4 files changed, 344 insertions(+), 1 deletion(-)

diff --git a/os/hal/platforms/STM32/TIMv1/icu_lld.c b/os/hal/platforms/STM32/TIMv1/icu_lld.c
index 11a10eb..26566b9 100644
--- a/os/hal/platforms/STM32/TIMv1/icu_lld.c
+++ b/os/hal/platforms/STM32/TIMv1/icu_lld.c
@@ -95,6 +95,35 @@ ICUDriver ICUD8;
ICUDriver ICUD9;
#endif

+/**
+ * @brief ICUD15 driver identifier.
+ * @note The driver ICUD15 allocates the timer TIM15 when enabled.
+ */
+#if STM32_ICU_USE_TIM15 || defined(__DOXYGEN__)
+ICUDriver ICUD15;
+#endif
+/**
+ * @brief ICUD16 driver identifier.
+ * @note The driver ICUD16 allocates the timer TIM16 when enabled.
+ */
+#if STM32_ICU_USE_TIM16 || defined(__DOXYGEN__)
+ICUDriver ICUD16;
+#endif
+/**
+ * @brief ICUD17 driver identifier.
+ * @note The driver ICUD17 allocates the timer TIM17 when enabled.
+ */
+#if STM32_ICU_USE_TIM17 || defined(__DOXYGEN__)
+ICUDriver ICUD17;
+#endif
+/**
+ * @brief ICUD19 driver identifier.
+ * @note The driver ICUD19 allocates the timer TIM19 when enabled.
+ */
+#if STM32_ICU_USE_TIM19 || defined(__DOXYGEN__)
+ICUDriver ICUD19;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -327,6 +356,94 @@ CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
}
#endif /* STM32_ICU_USE_TIM9 */

+#if STM32_ICU_USE_TIM15
+#if !defined(STM32_TIM15_HANDLER)
+#error "STM32_TIM15_HANDLER not defined"
+#endif
+/**
+ * @brief TIM15 compare interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_TIM15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD15);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM15 */
+
+#if STM32_ICU_USE_TIM16
+#if !defined(STM32_TIM16_HANDLER)
+#error "STM32_TIM16_HANDLER not defined"
+#endif
+/**
+ * @brief TIM16 compare interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_TIM16_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD16);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM16 */
+
+#if STM32_ICU_USE_TIM17
+#if !defined(STM32_TIM17_HANDLER)
+#error "STM32_TIM17_HANDLER not defined"
+#endif
+/**
+ * @brief TIM17 compare interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_TIM17_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD17);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM17 */
+
+#if STM32_ICU_USE_TIM19
+#if !defined(STM32_TIM19_HANDLER)
+#error "STM32_TIM19_HANDLER not defined"
+#endif
+/**
+ * @brief TIM19 compare interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_TIM19_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD19);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM19 */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/TIMv1/icu_lld.h b/os/hal/platforms/STM32/TIMv1/icu_lld.h
index 6c2c1b9..9c4972b 100644
--- a/os/hal/platforms/STM32/TIMv1/icu_lld.h
+++ b/os/hal/platforms/STM32/TIMv1/icu_lld.h
@@ -105,6 +105,42 @@
#endif

/**
+ * @brief ICUD15 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD15 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM15) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM15 FALSE
+#endif
+
+/**
+ * @brief ICUD16 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD16 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM16) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM16 FALSE
+#endif
+
+/**
+ * @brief ICUD17 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD17 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM17) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM17 FALSE
+#endif
+
+/**
+ * @brief ICUD19 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD19 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM19) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM19 FALSE
+#endif
+
+/**
* @brief ICUD1 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
@@ -152,6 +188,32 @@
#if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
#endif
+
+/**
+ * @brief ICUD15 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM15_IRQ_PRIORITY 7
+#endif
+/**
+ * @brief ICUD16 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM16_IRQ_PRIORITY 7
+#endif
+/**
+ * @brief ICUD19 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM17_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM17_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD19 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM19_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM19_IRQ_PRIORITY 7
+#endif
/** @} */

/*===========================================================================*/
@@ -186,10 +248,28 @@
#error "TIM9 not present in the selected device"
#endif

+#if STM32_ICU_USE_TIM15 && !STM32_HAS_TIM15
+#error "TIM15 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM16 && !STM32_HAS_TIM16
+#error "TIM16 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM17 && !STM32_HAS_TIM17
+#error "TIM17 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM19 && !STM32_HAS_TIM19
+#error "TIM19 not present in the selected device"
+#endif
+
#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 && \
!STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 && \
!STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 && \
- !STM32_ICU_USE_TIM9
+ !STM32_ICU_USE_TIM9 && !STM32_ICU_USE_TIM15&& \
+ !STM32_ICU_USE_TIM16 && !STM32_ICU_USE_TIM17 && \
+ !STM32_ICU_USE_TIM19
#error "ICU driver activated but no TIM peripheral assigned"
#endif

@@ -228,6 +308,26 @@
#error "Invalid IRQ priority assigned to TIM9"
#endif

+#if STM32_ICU_USE_TIM15 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM15_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM15"
+#endif
+
+#if STM32_ICU_USE_TIM16 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM16_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM16"
+#endif
+
+#if STM32_ICU_USE_TIM17 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM17_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM17"
+#endif
+
+#if STM32_ICU_USE_TIM19 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM19_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM19"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -393,6 +493,22 @@ extern ICUDriver ICUD8;
extern ICUDriver ICUD9;
#endif

+#if STM32_ICU_USE_TIM15 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD15;
+#endif
+
+#if STM32_ICU_USE_TIM16 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD16;
+#endif
+
+#if STM32_ICU_USE_TIM17 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD17;
+#endif
+
+#if STM32_ICU_USE_TIM19 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD19;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/platforms/STM32F37x/stm32_isr.h b/os/hal/platforms/STM32F37x/stm32_isr.h
index 30d9816..54978f7 100644
--- a/os/hal/platforms/STM32F37x/stm32_isr.h
+++ b/os/hal/platforms/STM32F37x/stm32_isr.h
@@ -70,6 +70,10 @@
#define STM32_TIM7_HANDLER Vector11C
#define STM32_TIM12_HANDLER VectorEC
#define STM32_TIM14_HANDLER VectorF4
+#define STM32_TIM15_HANDLER VectorA0
+#define STM32_TIM16_HANDLER VectorA4
+#define STM32_TIM17_HANDLER VectorA8
+#define STM32_TIM19_HANDLER Vector178

#define STM32_TIM2_NUMBER 28
#define STM32_TIM3_NUMBER 29
@@ -79,6 +83,10 @@
#define STM32_TIM7_NUMBER 55
#define STM32_TIM12_NUMBER 43
#define STM32_TIM14_NUMBER 45
+#define STM32_TIM15_NUMBER 24
+#define STM32_TIM16_NUMBER 25
+#define STM32_TIM17_NUMBER 26
+#define STM32_TIM19_NUMBER 78

/*
* USART units.
diff --git a/os/hal/platforms/STM32F37x/stm32_rcc.h b/os/hal/platforms/STM32F37x/stm32_rcc.h
index 607d9d7..e6624fd 100644
--- a/os/hal/platforms/STM32F37x/stm32_rcc.h
+++ b/os/hal/platforms/STM32F37x/stm32_rcc.h
@@ -732,6 +732,108 @@
* @api
*/
#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
+/**
+ * @brief Enables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Disables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Resets the TIM15 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
+/** @} */
+
+/**
+ * @brief Enables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Disables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Resets the TIM16 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
+/** @} */
+
+/**
+ * @brief Enables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Disables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Resets the TIM17 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+/** @} */
+
+/**
+ * @brief Enables the TIM19 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM19(lp) rccEnableAPB2(RCC_APB2ENR_TIM19EN, lp)
+
+/**
+ * @brief Disables the TIM19 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM19(lp) rccDisableAPB2(RCC_APB2ENR_TIM19EN, lp)
+
+/**
+ * @brief Resets the TIM19 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM19() rccResetAPB2(RCC_APB2RSTR_TIM19RST)
/** @} */

/**
--
1.8.1.2

There are problems with this, the main one is that TIM 15,16 and 17 have their ISRs shared with TIM1 on the STM32F30x so the patch would conflict on that platform with GPT or PWM in case TIM1 is used.

Shared ISRs are the reason why not all timers are supported, a workaround for this would mean restructuring the HAL heavily in order to have separate ISRs for each sub-platform. Not impossible but not in 2.6.x.

Giovanni

Does this mean we can safely use the patch as long as we don't use TIM1 for anything? Also, will it work on F0?