ChibiOS Free Embedded RTOS

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static const SPIConfig spi2_conf = {
        NULL,
        GPIOE,          /* chip select */
        7,              /* chip select */
        SPI_CR1_BR_0 |  /* quarter of APB2 frequency */
        SPI_CR1_CRCEN   /* enable CRC */
};

void exchange(const void *txbuf, void *rxbuf, int size)
{
        uint16_t crc;

        spiAcquireBus(&SPID2);
        spiStart(&SPID2, &spi2_conf);
        spiSelect(&SPID2);
        spiExchange(&SPID2, size, txbuf, rxbuf);

        /* Read DR (CRC) to clear RXNE flag */
        crc = SPID2.spi->DR;
        (void) crc; /* to quiet compiler warning */

        spiUnselect(&SPID2);
        spiReleaseBus(&SPID2);
}

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5. Start the communication and sustain the communication until all but one byte or halfword
have been transmitted or received.
– In full duplex or transmitter-only mode, when the transfers are managed by
software, when writing the last byte or half word to the Tx buffer, set the
CRCNEXT bit in the SPI_CR1 register to indicate that the CRC will be transmitted
after the transmission of the last byte.
– In receiver only mode, set the bit CRCNEXT just after the reception of the second
to last data to prepare the SPI to enter in CRC Phase at the end of the reception of
the last data. CRC calculation is frozen during the CRC transfer.
6. After the transfer of the last byte or half word, the SPI enters the CRC transfer and
check phase. In full duplex mode or receiver-only mode, the received CRC is
compared to the SPI_RXCRCR value. If the value does not match, the CRCERR flag in
SPI_SR is set and an interrupt can be generated when the ERRIE bit in the SPI_CR2
register is set.

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while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0);
dmaStreamClearInterrupt(dmastp);

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void DMA1_Stream3_IRQHandler(void)
{
    uint8_t iTemp;

    while (!(SPI2->SR & SPI_I2S_FLAG_TXE)); /* wait until transmit complete */
    while (SPI2->SR & SPI_I2S_FLAG_BSY); /* wait until SPI is not busy */

    iTemp = SPI2->DR;
    DMA_ClearITPendingBit(DMA1_Stream3, DMA_IT_TCIF3);
}