ChibiOS Free Embedded RTOS

Hi guys,
I also posted this in ST's E2E support but there doesn't seem to be anyone about who's worked with this so thought I would try my luck here.

I've been racking my head trying to make sense of how to correctly configure the I2S Hardware to interface with the MP45DT02 microphone. I've been looking at ST's waverecorder.c for inspiration but I think some iffy comments are really throwing me off. I was hoping someone here would be able to help me make sense of the configuration - I basically want to be able to understand how to select the appropriate values for the registers.

So, say I desire to ultimately get 16 bit 16 kHz PCM audio. This means, with 64 decimation, I need to sample the PDM microphone at 64 * 16 kHz = 1.024 MHz.

The I2S needs to be configured to do this and I understand how (in ST's example):
HSE_Frequency = 8 MHz
PLL_M = 8
PLLI2S_N = 258
PLLI2S_R = 3
Can give at 86 MHz clock to the I2S hardware. Its here where it all goes to pot. How do I configure I2S with an input of 86 MHz (or otherwise) to sample PDM at 1.024 MHz.

Would I be right in saying a 1.024 MHz clock for PDM is the same as considering 16 bit I2S to be sampled at 64 kHz? ST's code comments throw me at this point as they state:
* - Master clock output (MCKO): ON
* - Audio sampling freq (KHz) : 48

but then the I2S init function gets:
I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
I2S_InitStructure.I2S_AudioFreq = 32000;

I feel the last formula and diagram on page 893 of the reference manual should be helpful but I'm currently struggling how the tie together, especially with the two divisions of factor 2 in the formula. (I've never worked with audio before).

Any help appreciated.

Hi,

At page 889 there is table 126 where the values you posted are included and look correct.

Giovanni

Thanks Giovanni,
But I'm still unsure of what I2S clock frequency I need to be aiming for to achieve 1.024 MHz PDM sampling.
I can set the PLL OK, but then I've got:
I2SDIV, ODD, MCKOE, I2SMOD, CHLEN - basically all the I2S configuration to worry about.
So the formula on page 893 for instance is:
FS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide.

This would presumably be the rate of sampled data, i.e. the sampling rate of the 16-bit data? (So the I2S output clock would be 16 * Fs)
So I would be using:
1.024 MHz /16= 86 MHz / [(16*2)*((2*I2SDIV)+ODD))]
to calculate I2SDIV?

Just when I plug the values ST suggest they are using in the comments its miles off.

Hmm stumbled across the answer to one of my problems... why 32 kHz sampling rate works. Since I2S is 2 channel, 32 kHz audio sampling results in a clock of twice that rate. That makes some of the math a lot clearer. Also grabbed the source for the stdperiph_lib, which I'll review when I get a chance.

Sorry to resurrect an old post but I had shelved this project for a while due to other commitments. Recently I found the time to look into it again, and stumbled across this thread in one of my searches.

I put a post together detailing how to sample the MP45DT02 and use the PDM data. It can be found at the following link if anyone is interested: https://www.theunterminatedstring.com/probing-pdm/

Hi,

Thanks, good to know

Giovanni