STM32F0XX ADC Configuration Code Problem?
Posted: Sat Oct 18, 2014 3:45 am
Hello,
As I read through the code in adc_llc.c, I found the following snippet:
However, as I read the documentation from ST, the ADCSW bit in RCC->CFGR3 is obselete:
Another problem is that, I don't understand why bit 12 is set (the 0x00001000). The document says:
Could someone explain these? Thanks.
As I read through the code in adc_llc.c, I found the following snippet:
Code: Select all
#if STM32_ADCSW == STM32_ADCSW_HSI14
/* Clock from HSI14, no need for jitter removal.*/
ADC1->CFGR2 = 0x00001000;
#else
#if STM32_ADCPRE == STM32_ADCPRE_DIV2
ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2;
#else
ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4;
#endif
However, as I read the documentation from ST, the ADCSW bit in RCC->CFGR3 is obselete:
Obsolete setting. To be kept at reset value, connecting the HSI14 clock to the ADC
asynchronous clock input. Proper ADC clock selection is done inside the ADC_CFGR2 (refer
to Section 12.11.5: ADC configuration register 2 (ADC_CFGR2) on page 198).
Another problem is that, I don't understand why bit 12 is set (the 0x00001000). The document says:
Bits 29:0 Reserved, must be kept at reset value.
Could someone explain these? Thanks.