[NEWS]Very High Resolutions in Tickless Mode
Posted: Mon Dec 01, 2014 11:42 am
Hi all,
I wanted to signal a "breakthrough" achieved in the RT kernel starting from revision 7551.
Arbitrary High System Time Resolution
Now it is possible to set CH_CFG_ST_FREQUENCY to any frequency achievable by the used timer. Virtual timers and timeouts will work with the specified resolution.
There are things to consider when pushing the frequency:
1) The time conversion macros like MS2ST() can fail because integer overflows in the 32bits range used by the macros, I am considering allowing 64 bits math there. Constant expressions should not result in actual 64 bits arithmetic code in the system but I have to reason some more about it.
2) Special care must be taken in choosing the value for CH_CFG_ST_TIMEDELTA. This value represents the "uncertainty" level because system jitter. Basically the value is the number of cycles of acceptable jitter in the VTs subsystem. The value is a time interval expressed in system ticks that must be greater than: Longer VT callback routine + time spent in fast IRQs + safety number of cycles.
I tested on an F4 using CH_CFG_ST_FREQUENCY=4000000 and CH_CFG_ST_TIMEDELTA=16, the test suite passes using those values. Note that times specified for VTs can have an error up to CH_CFG_ST_TIMEDELTA*2 cycles (in excess).
Being the matter complex, frequencies in excess of 100kHz are only recommended in case of real necessity of such high resolutions.
Giovanni
I wanted to signal a "breakthrough" achieved in the RT kernel starting from revision 7551.
Arbitrary High System Time Resolution
Now it is possible to set CH_CFG_ST_FREQUENCY to any frequency achievable by the used timer. Virtual timers and timeouts will work with the specified resolution.
There are things to consider when pushing the frequency:
1) The time conversion macros like MS2ST() can fail because integer overflows in the 32bits range used by the macros, I am considering allowing 64 bits math there. Constant expressions should not result in actual 64 bits arithmetic code in the system but I have to reason some more about it.
2) Special care must be taken in choosing the value for CH_CFG_ST_TIMEDELTA. This value represents the "uncertainty" level because system jitter. Basically the value is the number of cycles of acceptable jitter in the VTs subsystem. The value is a time interval expressed in system ticks that must be greater than: Longer VT callback routine + time spent in fast IRQs + safety number of cycles.
I tested on an F4 using CH_CFG_ST_FREQUENCY=4000000 and CH_CFG_ST_TIMEDELTA=16, the test suite passes using those values. Note that times specified for VTs can have an error up to CH_CFG_ST_TIMEDELTA*2 cycles (in excess).
Being the matter complex, frequencies in excess of 100kHz are only recommended in case of real necessity of such high resolutions.
Giovanni