ChibiOS Free Embedded RTOS

Hi,

I have a timing critical section. Getting an interrupt halfway through will corrupt data. I need to turn off interrupts. I thought I'd need chSysLock but I cannot determine what it does from the documentation:

Enters the kernel lock mode.

What do I need to do to disable interrupts?

Hi,

chSysLock();
...
chSysUnlock();

Giovanni

Ok. Thanks, but do you see that adding a "on most implementations this will disable interrupts" or some such explanation helps users?

chSysLock -> port_lock ->
Does not explicitly disable all interrupts on STM32. It elevates the current interrupt priority mask to some level.
If compiled with CORTEX_SIMPLIFIED_PRIORITY it will be __disable_irq().

port_disable does state to disable all maskable interrupts in the documentations.
Here is an port docu page. Cortex M for gcc.
http://chibios.sourceforge.net/docs/por ... o_r_e.html

You linked me to the "ARM-V7" port page. I have a cortex M0. People who already know such a thing think it is obvious. It is not.

Similarly, I can follow the implementation through defines ending up on the page you mention, or, as I'd probably follow the implementation in my source directory on MY machine I'd end up with the "asm basepri" statement. For someone not fluent in the ARM architecture, for someone preferring to use the abstractions of chibios, that would mean I'd have to delve into the ARM ARCHITECTURE REFERENCE 1000+ pages. And find what I'm looking for.

From my point-of-view, I cannot find any documentation about "chSysLock".

Look, I'm not "ordering" you guys to go in and fix that documentation "right now!!", but it is a point to keep in mind: put in a bit more information for those that need to USE the stuff at THEIR level of abstraction. A quick: "this effectively disables interrupts on most systems" will in this instance clarify "chSysLock" a lot for most people.

They are the docs of the cortex m4. However, the m0 is equal in he basics. The m4 has some more advanced instructions. I guess (do not know for sure) the interrupt model is equal.

rew wrote:You linked me to the "ARM-V7" port page. I have a cortex M0. People who already know such a thing think it is obvious. It is not.

That is a problem of all fields. Sometimes, somewhere you're going to find ambiguous documentations. And you'll have to dig or ask.
If you look at the portable docs, it says: Enters the kernel lock mode.
Which does not say the interrupts will be disabled. It is just an abstract definition of a kernel mode.
If you look at the v6 or v7 docs it says:
Usually this function just disables interrupts but may perform more actions. With a note telling you it elevates the interrupt priority mask on v7 mode. Blocking any interrupts below CORTEX_BASEPRI_KERNEL.
Which is 1 if I'm looking correctly. So any interrupts more important than 1 will still run. Usually only the exceptions, but the nvic is configurable.

However, on v6, it runs cpsid. Change Processor State, Disable Interrupts.
Be aware that in lock mode, you can miss a systick because that interrupt won't be run.

There are some configs that modify the behavior of chSysLock and the interrupt epilogues. This is the lower level of chibios, you need to be familiar with ARM, your compiler and chibios to know all the details. Unfortunately.

Just don't think "interrupts", think "critical zones".

You don't need to know how a critical zone is actually implemented, this is why interrupts are never mentioned.

Giovanni

Jeroen3 wrote:There are some configs that modify the behavior of chSysLock and the interrupt epilogues. This is the lower level of chibios, you need to be familiar with ARM, your compiler and chibios to know all the details. Unfortunately.

As a user I want to know:
* Does something architecture dependent. Usually does something to disable interrupts, or "most interrupts".
* Read the implementation documtentation *HERE*.
* Is used for critical zones.

As a user, having asked on the forum and having been told:

Which is 1 if I'm looking correctly. So any interrupts more important than 1 will still run. Usually only the exceptions, but the nvic is configurable.

I'm starting to be afraid: My code is timing pulses from the DHT: 30 or 70 microseconds for a 0 or a 1. A 40 microsecond interrupt will change a "perfect 1" into a "perfect 0". So ANY interrupt is a problem.

I need to know: "regular interrupts from devices will be blocked, only exceptions will still run".

I'm LIKELY to miss systick interrupts, by my calculations the data-transmission phase of the sensor takes about 3ms, depending on the data. (25.5 degrees takes .25ms longer than 25.6 degrees.) I might miss serial communcations too. I don't know how the lower level is implemented. DMA buffer or not. If not, I'll lose UART interrupts and bytes. I'll have to deal with that.

You need to read "kernel concepts" in the documentation and understand the system state machine image you will find there.

If you need to implement low jitter interrupt handlers then look for "fast interrupts", in the cortex-m port priority levels 0 and 1 are reserved as fast interrupts and are never affected by device driver ISRs and system critical zones (that partial disabling thing).

The limitation is that from fast ISRs you cannot call RTOS functions, what you can do is to trigger a "normal interrupt" and delegate the RTOS calling to another ISR.

The above are pretty "advanced" topics.

Giovanni