For now I've implemented a horrible hack which sets a timeout on the busy-waits related to LSE:
Code: Select all
Index: os/hal/platforms/STM32F4xx/hal_lld.c
===================================================================
--- os/hal/platforms/STM32F4xx/hal_lld.c (revision 8349)
+++ os/hal/platforms/STM32F4xx/hal_lld.c (working copy)
@@ -68,9 +68,10 @@
/* No LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON;
#endif
- while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ int waitCounter = 0;
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0 && ++waitCounter <LSE_TIMEOUT)
; /* Waits until LSE is stable. */
-#endif
+#endif /* STM32_LSE_ENABLED */
#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
Index: os/hal/platforms/STM32/RTCv2/rtc_lld.c
===================================================================
--- os/hal/platforms/STM32/RTCv2/rtc_lld.c (revision 8349)
+++ os/hal/platforms/STM32/RTCv2/rtc_lld.c (working copy)
@@ -58,7 +58,10 @@
*
* @notapi
*/
-#define rtc_lld_apb1_sync() {while ((RTCD1.id_rtc->ISR & RTC_ISR_RSF) == 0);}
+#define rtc_lld_apb1_sync() { \
+ int counter = 0; \
+ while ((RTCD1.id_rtc->ISR & RTC_ISR_RSF) == 0 && ++counter <LSE_TIMEOUT);\
+ }
/**
* @brief Beginning of configuration procedure.
@@ -67,7 +70,8 @@
*/
#define rtc_lld_enter_init() { \
RTCD1.id_rtc->ISR |= RTC_ISR_INIT; \
- while ((RTCD1.id_rtc->ISR & RTC_ISR_INITF) == 0) \
+ int counter = 0; \
+ while ((RTCD1.id_rtc->ISR & RTC_ISR_INITF) == 0 && ++counter <LSE_TIMEOUT)\
; \
}
Index: os/hal/platforms/STM32/RTCv2/rtc_lld.h
===================================================================
--- os/hal/platforms/STM32/RTCv2/rtc_lld.h (revision 8349)
+++ os/hal/platforms/STM32/RTCv2/rtc_lld.h (working copy)
@@ -36,6 +36,11 @@
/*===========================================================================*/
/**
+ * this hack is about surviving lack of LSE (32kHz osc) part of RTC
+ */
+#define LSE_TIMEOUT 1000000
+
+/**
* @brief Two alarm comparators available on STM32F4x and STM32F2x.
*/
#if !defined(STM32F0XX)