ChibiOS Free Embedded RTOS

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Open On-Chip Debugger 0.9.0-dev-00415-g2d4ae3f-dirty (2015-06-12-17:54)
Licensed under GNU GPL v2
For bug reports, read
   http://openocd.org/doc/doxygen/bugs.html
Warn : Interface already configured, ignoring
Error: already specified hl_layout stlink
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 1800 kHz
srst_only separate srst_nogate srst_open_drain connect_deassert_srst
adapter_nsrst_delay: 100
Info : clock speed 1800 kHz
Error: open failed
in procedure 'init' 
in procedure 'ocd_bouncer'

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# This is an motocontrol board with a single STM32F746IGT chip.
# ### To be updated ### http://www.st.com/internet/evalboard/product/.jsp
#

# This is for using the onboard STLINK/V2-1
source [find interface/stlink-v2-1.cfg]

transport select hla_swd

# increase working area to 256KB
set WORKAREASIZE 0x40000

# chip name
set CHIPNAME STM32F746

source [find target/stm32f7x.cfg]

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# script for stm32f7x family

#
# stm32f7 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME stm32f7x
}

   set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 128kB
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x20000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      # See STM Document RM0385
      # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
      set _CPUTAPID 0x5ba00477
   } {
      set _CPUTAPID 0x5ba02477
   }
}

swj_newdap $_CHIPNAME cpu -irlen 1 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

if { [info exists BSTAPID] } {
   set _BSTAPID1 $BSTAPID
} else {
  # See STM Document RM0385
  # Section 40.6.1
  # STM32F75xxG
  set _BSTAPID1 0x06449041
}

if {[using_jtag]} {
 swj_newdap $_CHIPNAME bs -irlen 2 -expected-id $_BSTAPID1
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f7x 0 0 0 0 $_TARGETNAME

# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
adapter_khz 1800

# use hardware reset, connect under reset
reset_config srst_only srst_nogate

adapter_nsrst_delay 100
if {[using_jtag]} {
 jtag_ntrst_delay 100
}

if {![using_hla]} {
   # if srst is not fitted use SYSRESETREQ to
   # perform a soft reset
   cortex_m reset_config sysresetreq
}

proc stm32f7x_default_reset_start {} {
   # Reset clock is HSI (16 MHz)
   adapter_khz 1000
}

$_TARGETNAME configure -event examine-end {
   # Enable debug during low power modes (uses more power)
   # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
   mmw 0xE0042004 0x00000007 0

   # Stop watchdog counters during halt
   # DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
   mww 0xE0042008 0x00001800
}

$_TARGETNAME configure -event trace-config {
   # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
   # change this value accordingly to configure trace pins
   # assignment
   mmw 0xE0042004 0x00000020 0
}

$_TARGETNAME configure -event reset-init {
   # Configure PLL to boost clock to HSI x 4 (64 MHz)
   mww 0x40023804 0x08012008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
   mww 0x40023C00 0x00000102   ;# FLASH_ACR = PRFTBE | 2(Latency)
   mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
   sleep 10                    ;# Wait for PLL to lock
   mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
   mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL

   # Boost JTAG frequency
   adapter_khz 8000
}

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# reset_config srst_only srst_nogate
reset_config none separate

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Loading section startup, size 0x200 lma 0x8000000
Loading section .text, size 0xc1d0 lma 0x8000200
Loading section .rodata, size 0x19fc lma 0x800c3d0
Loading section .data, size 0xdc lma 0x800ddcc
Start address 0x200201, load size 57000
Transfer rate: 36 KB/sec, 8142 bytes/write.
tbreak main
Temporary breakpoint 1 at 0x20c0f0: file main.c, line 140.
continue