STM32F4 clock configuration

[heiko]

Hi,

on an STM32F407, I changed the clock configuration as follows, to achieve a system clock of 144MHz instead of the standard 168MHz (in order to be able to use the maximum clock for ADC):

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#define STM32_HSE_ENABLED                   TRUE // HSE 8MHz
#define STM32_CLOCK48_REQUIRED              TRUE
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE                    6
#define STM32_PLLN_VALUE                    216
#define STM32_PLLP_VALUE                    2 // SYSCLK 144MHz
#define STM32_PLLQ_VALUE                    6 // 48MHz

However, when compiling, the USB frequency check in os/hal/ports/STM32/LLD/OTGv1/usb_lld.h throws the error "the USB OTG driver requires a 48MHz clock". This is because of

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#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)

which results in a float with my configuration.

I'd rather calculate the two values based on STM32_PLLCLKIN like this (changed the sequence of division and multiplication in os/hal/ports/STM32/STM32F4xx/hal.lld.h):

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//#define STM32_PLLVCO           (STM32_PLLCLKIN * STM32_PLLN_VALUE)
#define STM32_PLLVCO             ((STM32_HSECLK * STM32_PLLN_VALUE) / STM32_PLLM_VALUE)

//#define STM32_PLLI2SVCO        (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)
#define STM32_PLLI2SVCO          ((STM32_HSECLK * STM32_PLLI2SN_VALUE) / STM32_PLLM_VALUE)

to avoid dealing with the float.

I couldn't test this yet, but am I overlooking something? Could and should this be changed in ChibiOS in general? I could send a pull request or sth...

[Giovanni]

Hi,

I can see the problem, it will require a lot of changes and not just in the F4, there are all the other platforms to consider and also check for similar issues.

Putting this in queue. Submit patches if you want to go ahead, you suggestion looks OK at first glance.

Giovanni