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ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 4:54 pm
by duststorm
Hello,

I'm trying to use HAL only for a simple project on a STM32 nucleo-F446RE board.
A minimal example where I try to query two input pins using the ADC blocks.

Code: Select all

/*
*/

#include "hal.h"

/*
 ADC setup
*/
// Create buffer to store ADC results. This is
// one-dimensional interleaved array
#define ADC_BUF_DEPTH 2 // depth of buffer
#define ADC_CH_NUM 2    // number of used ADC channels
static adcsample_t samples_buf[ADC_BUF_DEPTH * ADC_CH_NUM]; // results array for adc1

static ADCConfig adccfg = {0};


/*
 * Callback invoked when ADC conversion is done
 */
void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
  if (adcp->state == ADC_COMPLETE) {
    toggle_led();
  }
}

void adcerr(ADCDriver *adcp, adcerror_t err) {
}


#define ADC1_CH1 0
#define ADC1_CH2 2
static ADCConversionGroup adccg1 = {
   // this 3 fields are common for all MCUs
      // set to TRUE if need circular buffer, set FALSE otherwise
      TRUE,
      // number of channels
      (uint16_t)(ADC_CH_NUM),
      // callback function, set to NULL for begin
      adccb, //NULL,
      // error callback
      adcerr,
   // Resent fields are stm32 specific. They contain ADC control registers data.
   // Please, refer to ST manual RM0008.pdf to understand what we do.
      // CR1 register content, set to zero for begin
      0,
      // CR2 register content, set to zero for begin
      0,
      // SMRP1 register content, set to zero for begin
      0,
      // SMRP2 register content, set to zero for begin
      0,
      // SQR1 register content. Set channel sequence length
      ((ADC_CH_NUM - 1) << 20),
      // SQR2 register content, set to zero for begin
      0,
      // SQR3 register content. We must select 2 channels
      (ADC1_CH1 | (ADC1_CH2 << 5)),
};


void toggle_led(void) {
    if palReadPad(GPIOA, GPIOA_LED_GREEN) {
        palClearPad(GPIOA, GPIOA_LED_GREEN);
    } else {
        palSetPad(GPIOA, GPIOA_LED_GREEN);
    }
}

void loop(void) {
    toggle_led();

    // one-shot conversion
    adcConvert(&ADCD1, &adccg1, &samples_buf[0], ADC_BUF_DEPTH);

    osalThreadSleepMilliseconds(500);
}

/*
 * Application entry point.
 */
int main(void) {

  /*
   * System initializations.
   * - HAL initialization, this also initializes the configured device drivers
   *   and performs the board-specific initializations.
   */
  halInit();

  /*
   * Enabling interrupts, initialization done.
   */
  osalSysEnable();

  /*
   * Setup adc input pins for analog input
   */
  palSetPadMode(GPIOA, GPIOA_PIN0, PAL_MODE_INPUT_ANALOG); // adc channel 0, pa0, adc1 ch1
  palSetPadMode(GPIOA, GPIOA_PIN1, PAL_MODE_INPUT_ANALOG); // adc channel 1, pa1, adc2 ch1

  // Enable led
  palSetPad(GPIOA, GPIOA_LED_GREEN);

  adcInit();  // not really necessary as halInit() already does this

  // Activate ADC1 peripheral
  adcStart(&ADCD1, &adccfg);


  /*
   * Main loop
   */
  while (true) {
    loop();
  }
}


With the debugger I could determine that the adcConvert() function was blocking in osalThreadSuspendS(), where it appears to keep iterating through the first osalSysUnlock() call in the while loop.

Comment out the adcConvert() statement, and the board runs fine and the led alternates. Add the statement in the main loop, and the board gets stuck in infinite wait.

I'm quite clueless, anybody has ideas?

I was first trying to do asynchronous conversion, but as the callbacks were never called, I reduced it to an inline conversion for testing.

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 4:59 pm
by duststorm
Don't know if this could shed some light, but here is

osalconf.h

Code: Select all

/*
    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

/*
  This config file is needed when using the OS-less OSAL component
*/

/**
 * @file    templates/halconf.h
 * @brief   Bare-metal OSAL configuration header.
 *
 * @addtogroup OSAL_CONF
 * @{
 */

#ifndef _OSALCONF_H_
#define _OSALCONF_H_

/**
 * @brief   Frequency in Hertz of the system tick.
 */
#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__)
#define OSAL_ST_FREQUENCY                   1000
#endif

/**
 * @brief   Enables OSAL assertions.
 */
#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define OSAL_DBG_ENABLE_ASSERTS             FALSE
#endif

/**
 * @brief   Enables OSAL functions parameters checks.
 */
#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define OSAL_DBG_ENABLE_CHECKS              FALSE
#endif

/**
 * @brief   OSAL initialization hook.
 */
#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__)
#define OSAL_INIT_HOOK() {                                                  \
}
#endif

/**
 * @brief   Idle loop hook macro.
 */
#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__)
#define OSAL_IDLE_HOOK() {                                                  \
}
#endif

#endif /* _OSALCONF_H_ */

/** @} */



mcuconf.h

Code: Select all

/*
    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#ifndef _MCUCONF_H_
#define _MCUCONF_H_

/*
 * STM32F4xx drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 15...0       Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

#define STM32F4xx_MCUCONF

/*
 * Define the MCU that we are using
 */
//#define STM32F446xx

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
/* Enable HSI Oscillator and activate PLL with HSI as source */
#define STM32_HSI_ENABLED                   TRUE
#define STM32_LSI_ENABLED                   TRUE
#define STM32_HSE_ENABLED                   FALSE
#define STM32_LSE_ENABLED                   FALSE
// Use 48MHz PLL multiplier output clock
#define STM32_CLOCK48_REQUIRED              TRUE
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSI
// PLL Parameters
// M (between 2 and 63)
#define STM32_PLLM_VALUE                    16
// N (between 192 and 432)
#define STM32_PLLN_VALUE                    360
// P (2, 4, 6 or 8)
#define STM32_PLLP_VALUE                    2
// Q (between 2 and 15)
#define STM32_PLLQ_VALUE                    7
// R (between 2 and 7) is only available on F446 devices
#define STM32_PLLR_VALUE                    2

#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV4
#define STM32_PPRE2                         STM32_PPRE2_DIV2
#define STM32_RTCSEL                        STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE                  8
#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE                 192
#define STM32_PLLI2SR_VALUE                 5
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE                 FALSE

/*
 * ADC driver system settings.
 */
// Use driver for STM32 "advanced" ADC found on F2, F4 and F7 sub-families
#define STM32_ADC_USE_ADC1                  TRUE
#define STM32_ADC_USE_ADC2                  TRUE
#define STM32_ADC_USE_ADC3                  TRUE
#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY         2
#define STM32_ADC_IRQ_PRIORITY              6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6

/*
 * DAC driver system settings.
 */
#define STM32_DAC_DUAL_MODE                 FALSE
#define STM32_DAC_USE_DAC1_CH1              TRUE
#define STM32_DAC_USE_DAC1_CH2              TRUE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 6)

/*
 * EXT driver system settings.
 */
#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
#define STM32_EXT_EXTI17_IRQ_PRIORITY       15
#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
#define STM32_EXT_EXTI22_IRQ_PRIORITY       15

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM1                  FALSE
#define STM32_GPT_USE_TIM2                  FALSE
#define STM32_GPT_USE_TIM3                  FALSE
#define STM32_GPT_USE_TIM4                  FALSE
#define STM32_GPT_USE_TIM5                  FALSE
#define STM32_GPT_USE_TIM9                  FALSE
#define STM32_GPT_USE_TIM11                 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY         7
#define STM32_GPT_TIM2_IRQ_PRIORITY         7
#define STM32_GPT_TIM3_IRQ_PRIORITY         7
#define STM32_GPT_TIM4_IRQ_PRIORITY         7
#define STM32_GPT_TIM5_IRQ_PRIORITY         7
#define STM32_GPT_TIM9_IRQ_PRIORITY         7
#define STM32_GPT_TIM11_IRQ_PRIORITY        7

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1                  FALSE
#define STM32_I2C_USE_I2C2                  FALSE
#define STM32_I2C_USE_I2C3                  FALSE
#define STM32_I2C_BUSY_TIMEOUT              50
#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY         5
#define STM32_I2C_I2C2_IRQ_PRIORITY         5
#define STM32_I2C_I2C3_IRQ_PRIORITY         5
#define STM32_I2C_I2C1_DMA_PRIORITY         3
#define STM32_I2C_I2C2_DMA_PRIORITY         3
#define STM32_I2C_I2C3_DMA_PRIORITY         3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

/*
 * I2S driver system settings.
 */
#define STM32_I2S_USE_SPI2                  FALSE
#define STM32_I2S_USE_SPI3                  FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY         10
#define STM32_I2S_SPI3_IRQ_PRIORITY         10
#define STM32_I2S_SPI2_DMA_PRIORITY         1
#define STM32_I2S_SPI3_DMA_PRIORITY         1
#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM1                  FALSE
#define STM32_ICU_USE_TIM2                  FALSE
#define STM32_ICU_USE_TIM3                  FALSE
#define STM32_ICU_USE_TIM4                  FALSE
#define STM32_ICU_USE_TIM5                  FALSE
#define STM32_ICU_USE_TIM9                  FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY         7
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
#define STM32_ICU_TIM5_IRQ_PRIORITY         7
#define STM32_ICU_TIM9_IRQ_PRIORITY         7

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_ADVANCED              FALSE
#define STM32_PWM_USE_TIM1                  FALSE
#define STM32_PWM_USE_TIM2                  FALSE
#define STM32_PWM_USE_TIM3                  FALSE
#define STM32_PWM_USE_TIM4                  FALSE
#define STM32_PWM_USE_TIM5                  FALSE
#define STM32_PWM_USE_TIM9                  FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY         7
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
#define STM32_PWM_TIM5_IRQ_PRIORITY         7
#define STM32_PWM_TIM9_IRQ_PRIORITY         7

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1             TRUE
#define STM32_SERIAL_USE_USART2             TRUE
#define STM32_SERIAL_USE_USART6             FALSE
#define STM32_SERIAL_USART1_PRIORITY        12
#define STM32_SERIAL_USART2_PRIORITY        12
#define STM32_SERIAL_USART6_PRIORITY        12

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1                  TRUE
#define STM32_SPI_USE_SPI2                  TRUE
#define STM32_SPI_USE_SPI3                  FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY         1
#define STM32_SPI_SPI2_DMA_PRIORITY         1
#define STM32_SPI_SPI3_DMA_PRIORITY         1
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
#define STM32_SPI_SPI3_IRQ_PRIORITY         10
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

/*
 * ST driver system settings.
 */
#define STM32_ST_IRQ_PRIORITY               8
#define STM32_ST_USE_TIMER                  2

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1               FALSE
#define STM32_UART_USE_USART2               FALSE
#define STM32_UART_USE_USART6               FALSE
#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY      12
#define STM32_UART_USART2_IRQ_PRIORITY      12
#define STM32_UART_USART6_IRQ_PRIORITY      12
#define STM32_UART_USART1_DMA_PRIORITY      0
#define STM32_UART_USART2_DMA_PRIORITY      0
#define STM32_UART_USART6_DMA_PRIORITY      0
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

/*
 * USB driver system settings.
 */
#define STM32_USB_USE_USB1                  TRUE
#define STM32_USB_USE_OTG1                  FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY         14
#define STM32_USB_OTG1_RX_FIFO_SIZE         512
#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE     128
#define STM32_USB_OTGFIFO_FILL_BASEPRI      0

/*
 * WDG driver system settings.
 */
#define STM32_WDG_USE_IWDG                  FALSE

#endif /* _MCUCONF_H_ */



I tried with both ADC_USE_MUTUAL_EXCLUSION on and off in halconf.h

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 5:12 pm
by RoccoMarco
Hi,
I think the problem could be that you have missed Software start bit in CR2. Note that there are some usefuls macro which could help. Take a look to testhal/STM32/STM32F4xx/ADC

Meanwhile you can try this:

Code: Select all

/*
 * ADC conversion group.
 * Mode:        Continuous, 2 channels, SW triggered.
 * Channels:    IN0 -> PA0, IN1 -> PA1.
 */
static const ADCConversionGroup adccg1 = {
  TRUE,
  ADC_CH_NUM,
  adccb,
  adcerr,
  0,
  ADC_CR2_SWSTART,
  0,
  ADC_SMPR2_SMP_AN0(ADC_SAMPLE_56), ADC_SMPR2_SMP_AN0 (ADC_SAMPLE_56),
  ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS),
  0,
  ADC_SQR3_SQ2_N(ADC_CHANNEL_IN0) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1)
};


If the problem is solved please use the checkbox button on top of this message to mark the topic as Solved. Otherwise we will try something else.
Ciao,
RM

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 5:34 pm
by duststorm
It seems to hang in the same place.

Code: Select all

static const ADCConversionGroup adccg1 = {
  TRUE,
  ADC_CH_NUM,
  adccb,
  adcerr,
  0,  // CR1
  ADC_CR2_SWSTART, //CR2
  0, // SMRP1
  ADC_SMPR2_SMP_AN0(ADC_SAMPLE_56), ADC_SMPR2_SMP_AN0 (ADC_SAMPLE_56), // SMRP2
  ADC_SQR1_NUM_CH(ADC_CH_NUM), // SQR1
  0, // SQR2
  ADC_SQR3_SQ2_N(ADC1_CH1) | ADC_SQR3_SQ1_N(ADC1_CH2) // SQR3
};


I'm not sure about SMRP2 and the SQR registers, though.
I also tried changing CR2 to ADC_CR2_SWSTART only, and leaving the rest, but same problem.

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 5:45 pm
by RoccoMarco
Can you share your project? I will give it a try.

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 5:47 pm
by RoccoMarco
Anyway the configuration you have used is quite different from mine (you can just replace mine with yours). The sequence and sample rate are wrong but I don't think this could be your problem. What version of ChibiOS are you using?

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 5:51 pm
by duststorm
https://drive.google.com/file/d/0B9CGNW ... sp=sharing

It uses latest stable chibios, but I added a board definition for the nucleo f446.
I don't know if it's any good, though.

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 5:54 pm
by RoccoMarco
There are too much uncertainties :mrgreen:
If you checkout trunk you can find the full support for stm32f446. I committed it few days ago.

If may I suggest, try to move the project on this new version and use the mcuconf and board files provided on main demo. Maybe this would solve your problem or maybe not. Anyway, we will reduce the uncertainties and make debugging simplified.

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 7:26 pm
by duststorm
I was eyeballing the trunk version before (with a few changes to my makefile I could compile with trunk), but indeed now I pulled in some very interesting looking changes that I didn't have yet :)
I have the code to the point where it compiles, but I need to wait until tomorrow until I'm able to test it.
I'll let you know how it goes.

Thank you very much! :)

Re: ADC conversion blocks in osless HAL

Posted: Tue May 03, 2016 7:34 pm
by RoccoMarco
:mrgreen: You are welcome.