SDC uSD/HC and eMMC on L476 mostly working

[Al B]

Hi,

Spent considerable time testing sdc on L476, so hope the following analysis and configuration notes and recommendations will be useful to others too. I believe these configuration recommendations would likely apply to other processors that use SDIO similar to L476's (e.g. F1, F4).

In summary, have been able to get eMMC (4G Micron BGA, v4.51 compliant) and uSD (8G Lexar, HC class 10) working for most functions over all CPU speed ranging from 0.5 to 80MHz !

However to do so, requires several knobs to all be set correctly (I.e. changed from the default values) otherwise catastrophic or subtle infrequent issues arise. Having the Chibios defaults set to these, and possibly having some internal checks to determine violations would potentially be very useful.

Also a few minor bugs needed to be fixed to get it working (see attached spreadsheet with detailed analysis and list of issues). However, in my opinion, the code for the main path looks very good.

The one major area that is not working, and I believe is needed, is sdcErase(), which at least for me, doesn't work for either uSD/HC or eMMC.
I made some minor fixes to HC block size/memory addr adjustment issue, but there are still seem to be other issues (wrong cmds for mmc, etc).

Next steps will be to verify using FatFS, and more exhaustive testing to write and verify read back (checkboard pattern tests and such).

Regards,
Al

[Giovanni]

Hi,

Thanks for the analysis, apparently we just to put a preprocessor check to keep frequencies within that 70% boundary.

Please keep us updated about your findings, the SDC driver is clearly not mature enough.

Giovanni

[Giovanni]

Hi,

I added a check to the driver regarding the maximum frequency and defaulted all timeouts to 1000, please let me know if other changes are required.

Note that I plan to make this change in trunk code only.

Giovanni

[Al B]

Hi Giovanni,

I have now implemented the sdcErase, and fixed up a few other minor sdc issues.
I'm just doing some more inspections and testing and clean on it and will submit in a few days.
It covers high and low speed MMC and SD v1 and v2, and inspected on SPI (but have no way to test SPI unfortunately).

I noticed the timeout changes, and think that the write TO is good, but that the read one is probably a bit long.
It doesn't make any difference on the success path, but had been thinking that 200 would have been good.
I also noticed the clock check and that is good, but I am trying to figure out how to ease that off a bit since it impacts overall throughput, particularly at lower CPU speeds.

Thanks,
Al