ChibiOS Free Embedded RTOS

Posted: **Tue Jul 26, 2016 6:48 pm**

Hi!

I have been trying to get USB FS up and running on my board with an STM32F746IGK6 under ChibiOS/RT 16.1 (latest commits).
The problem I am having is that the USB seems to start correctly, but no USB CDC port is detected. (I run Linux)
* I have tested with a previous F4 board that detects the USB correctly.
* I have checked so the D+/D- are correctly connected (same as the DISCOVERY board).
* I have checked so the clock is correct by timing LED blinks on an oscilloscope.

So what I did was, I copied the testhal for USB_CDC, and the board starts and goes past all the USB startup without problems.
I also checked so the board files are matching.

And if I check the SDU2 it seems that the SDU is ready.

Code: Select all

SDU2 = {
  vmt = 0x80086d8 <vmt>,
  event = {
    es_next = 0x200013f0 <SDU2+4>
  },
  state = SDU_READY,
  ibqueue = {
    waiting = {
      p_next = 0x200013f8 <SDU2+12>,
      p_prev = 0x200013f8 <SDU2+12> 
    },
    bcounter = 0,
    bwrptr = 0x20001460 <SDU2+116> "",
    brdptr = 0x20001460 <SDU2+116> "",
    btop = 0x20001668 <SDU2+636> "",  
    bsize = 260,             
    bn = 2,
    buffers = 0x20001460 <SDU2+116> "",
    ptr = 0x0,                         
    top = 0x0,
    notify = 0x203f11 <ibnotify>,
    link = 0x200013ec <SDU2>     
  },
  obqueue = {
    waiting = {
      p_next = 0x2000142c <SDU2+64>,
      p_prev = 0x2000142c <SDU2+64> 
    },
    bcounter = 2,
    bwrptr = 0x20001668 <SDU2+636> "",
    brdptr = 0x20001668 <SDU2+636> "",
    btop = 0x20001870 <SDU2+1156> "\270\213",
    bsize = 260,
    bn = 2,     
    buffers = 0x20001668 <SDU2+636> "",
    ptr = 0x0,                         
    top = 0x0,
    notify = 0x203f31 <obnotify>,
    link = 0x200013ec <SDU2>     
  },
  ib = '\000' <repeats 519 times>,
  ob = '\000' <repeats 519 times>,
  config = 0x8008bb8 <serusbcfg>
}

And the USB says that its state is ready:

Code: Select all

USBD2 = {
  state = USB_READY,
  config = 0x8008ba8 <usbcfg>,
  transmitting = 0,
  receiving = 0,
  epc = {0x800886c <ep0config>, 0x0, 0x0, 0x0, 0x0, 0x0},
  in_params = {0x200013ec <SDU2>, 0x200013ec <SDU2>, 0x0, 0x0, 0x0},
  out_params = {0x200013ec <SDU2>, 0x0, 0x0, 0x0, 0x0},
  ep0state = USB_EP0_WAITING_SETUP,
  ep0next = 0x0,
  ep0n = 0,
  ep0endcb = 0x0,
  setup = "\000\000\000\000\000\000\000",
  status = 0,
  address = 0 '\000',
  configuration = 0 '\000',
  saved_state = USB_UNINIT,
  otg = 0x40040000,
  otgparams = 0x8008890 <hsparams>,
  pmnext = 272,
  txpending = 0,
  wait = 0x20000f98 <USBD2+136>,
  tr = 0x20000f98 <USBD2+136>,
  wa_pump = {2305851805843590368, 2305861408853590018, 2305857165962774528, 2305860567174251388,
    2305860107461787651, 2305860344238575552, 18446744069951459268, 0, 18446744069414584322,    
    4058744095665, 4294968241, 945, 6148914691236517205 <repeats 32 times>, 2305861839781975381,
    6148914690341736208, 6148914691236517205, 6148914691236517205, 9028370580198741,            
    240191980126426453, 2305860155260014880, 9036529588531889, 2305860104615187797, 
    2305860156154795349, 9109784548605984, 2305860103720406936, 9133630743908248, 2305859570701634556,
    9133304326393616, 4612811919765886293, 9040429953584912, 9010751729569688}                        
}

But as described there is no USB connection detected and dmesg doesn't report any new USB connected.

Any recommendation on how to debug this as ChibiOS reports that everything is OK, but nothing happens on the PC side?

Thanks!

//Emil

Posted: **Tue Jul 26, 2016 7:08 pm**

I have no immediate way to test on Linux. It used to work last time I tried, can anybody confirm?

Giovanni

Posted: **Tue Jul 26, 2016 7:37 pm**

Note that the driver is USB_READY, this means that the device has not been enumerated, it should be USB_ACTIVE. You could attach it to a windows boc for confirmation.

I think you have a problem in GPIO setup, alternatively clocks.

Giovanni

Posted: **Tue Jul 26, 2016 8:00 pm**

Thanks for the tip!

On clocks:
I completely copied the F7 DISCOVERY there, my board also have a 25 MHz oscillator.
And I am using the same clocks else. The only difference is that I do not have the LSE, so I switched to the LSI -- should this matter (I think not)?

On the GPIO:
I copied here as well (and have the same board configuration), the only difference is that VBUS is on a different pin and ID is not connected as I will not use HOST mode.

Can you see an error in this?

Thanks!

Posted: **Tue Jul 26, 2016 8:42 pm**

I have now also tested it on a windows machine, and it is the same thing there.

I am starting to suspect a bad solder joint somewhere.
Not so funny to try and fix on this card though :roll:

Posted: **Tue Jul 26, 2016 8:58 pm**

I would double check the board files and clocks.

Giovanni

Posted: **Tue Jul 26, 2016 10:26 pm**

I have now went through the RM and checked so the clock generation is correct (and cross-checked with STM32CubeMX).
The output of PLLQ is 48 MHz as required by the USB peripheral and AHB, APB1 and APB2 are within bounds (216 MHz, 54 MHz and 108 MHz).

On the D+ and D- (PA12/ PA11) lines I have double checked the AF values (that should be 10 for both pins to have OTG FS functionality), speed settings, mode and pu/pd resistors and it is correct.

My mcuconf.h for reference:

Code: Select all

/*
    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#ifndef _MCUCONF_H_
#define _MCUCONF_H_

/*
 * STM32F4xx drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 15...0       Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

#define STM32F7xx_MCUCONF

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE                 FALSE
#define STM32_HSI_ENABLED                   TRUE
#define STM32_LSI_ENABLED                   TRUE
#define STM32_HSE_ENABLED                   TRUE
#define STM32_LSE_ENABLED                   FALSE
#define STM32_CLOCK48_REQUIRED              TRUE
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE                    25
#define STM32_PLLN_VALUE                    432
#define STM32_PLLP_VALUE                    2
#define STM32_PLLQ_VALUE                    9
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV4
#define STM32_PPRE2                         STM32_PPRE2_DIV2
#define STM32_RTCSEL                        STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE                  25
#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV4
#define STM32_I2SSRC                        STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE                 192
#define STM32_PLLI2SP_VALUE                 4
#define STM32_PLLI2SQ_VALUE                 4
#define STM32_PLLI2SR_VALUE                 4
#define STM32_PLLSAIN_VALUE                 192
#define STM32_PLLSAIP_VALUE                 4
#define STM32_PLLSAIQ_VALUE                 4
#define STM32_PLLSAIR_VALUE                 4
#define STM32_PLLSAIDIVR                    STM32_PLLSAIDIVR_OFF
#define STM32_SAI1SEL                       STM32_SAI1SEL_OFF
#define STM32_SAI2SEL                       STM32_SAI2SEL_OFF
#define STM32_USART1SEL                     STM32_USART1SEL_PCLK2
#define STM32_USART2SEL                     STM32_USART2SEL_PCLK1
#define STM32_USART3SEL                     STM32_USART3SEL_PCLK1
#define STM32_UART4SEL                      STM32_UART4SEL_PCLK1
#define STM32_UART5SEL                      STM32_UART5SEL_PCLK1
#define STM32_USART6SEL                     STM32_USART6SEL_PCLK2
#define STM32_UART7SEL                      STM32_UART7SEL_PCLK1
#define STM32_UART8SEL                      STM32_UART8SEL_PCLK1
#define STM32_I2C1SEL                       STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL                       STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL                       STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL                       STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL                        STM32_CECSEL_LSE
#define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL48CLK
#define STM32_SRAM2_NOCACHE                 FALSE

/*
 * ADC driver system settings.
 */
#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1                  FALSE
#define STM32_ADC_USE_ADC2                  FALSE
#define STM32_ADC_USE_ADC3                  FALSE
#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY         2
#define STM32_ADC_ADC2_DMA_PRIORITY         2
#define STM32_ADC_ADC3_DMA_PRIORITY         2
#define STM32_ADC_IRQ_PRIORITY              6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6

/*
 * CAN driver system settings.
 */
#define STM32_CAN_USE_CAN1                  FALSE
#define STM32_CAN_USE_CAN2                  FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY         11
#define STM32_CAN_CAN2_IRQ_PRIORITY         11

/*
 * DAC driver system settings.
 */
#define STM32_DAC_DUAL_MODE                 FALSE
#define STM32_DAC_USE_DAC1_CH1              FALSE
#define STM32_DAC_USE_DAC1_CH2              FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 6)

/*
 * EXT driver system settings.
 */
#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
#define STM32_EXT_EXTI17_IRQ_PRIORITY       15
#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
#define STM32_EXT_EXTI20_IRQ_PRIORITY       6
#define STM32_EXT_EXTI21_IRQ_PRIORITY       15
#define STM32_EXT_EXTI22_IRQ_PRIORITY       15

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM1                  FALSE
#define STM32_GPT_USE_TIM2                  FALSE
#define STM32_GPT_USE_TIM3                  FALSE
#define STM32_GPT_USE_TIM4                  FALSE
#define STM32_GPT_USE_TIM5                  FALSE
#define STM32_GPT_USE_TIM6                  FALSE
#define STM32_GPT_USE_TIM7                  FALSE
#define STM32_GPT_USE_TIM8                  FALSE
#define STM32_GPT_USE_TIM9                  FALSE
#define STM32_GPT_USE_TIM11                 FALSE
#define STM32_GPT_USE_TIM12                 FALSE
#define STM32_GPT_USE_TIM14                 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY         7
#define STM32_GPT_TIM2_IRQ_PRIORITY         7
#define STM32_GPT_TIM3_IRQ_PRIORITY         7
#define STM32_GPT_TIM4_IRQ_PRIORITY         7
#define STM32_GPT_TIM5_IRQ_PRIORITY         7
#define STM32_GPT_TIM6_IRQ_PRIORITY         7
#define STM32_GPT_TIM7_IRQ_PRIORITY         7
#define STM32_GPT_TIM8_IRQ_PRIORITY         7
#define STM32_GPT_TIM9_IRQ_PRIORITY         7
#define STM32_GPT_TIM11_IRQ_PRIORITY        7
#define STM32_GPT_TIM12_IRQ_PRIORITY        7
#define STM32_GPT_TIM14_IRQ_PRIORITY        7

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1                  FALSE
#define STM32_I2C_USE_I2C2                  FALSE
#define STM32_I2C_USE_I2C3                  FALSE
#define STM32_I2C_USE_I2C4                  FALSE
#define STM32_I2C_BUSY_TIMEOUT              50
#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C4_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C4_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2C_I2C1_IRQ_PRIORITY         5
#define STM32_I2C_I2C2_IRQ_PRIORITY         5
#define STM32_I2C_I2C3_IRQ_PRIORITY         5
#define STM32_I2C_I2C4_IRQ_PRIORITY         5
#define STM32_I2C_I2C1_DMA_PRIORITY         3
#define STM32_I2C_I2C2_DMA_PRIORITY         3
#define STM32_I2C_I2C3_DMA_PRIORITY         3
#define STM32_I2C_I2C4_DMA_PRIORITY         3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM1                  FALSE
#define STM32_ICU_USE_TIM2                  FALSE
#define STM32_ICU_USE_TIM3                  FALSE
#define STM32_ICU_USE_TIM4                  FALSE
#define STM32_ICU_USE_TIM5                  FALSE
#define STM32_ICU_USE_TIM8                  FALSE
#define STM32_ICU_USE_TIM9                  FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY         7
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
#define STM32_ICU_TIM5_IRQ_PRIORITY         7
#define STM32_ICU_TIM8_IRQ_PRIORITY         7
#define STM32_ICU_TIM9_IRQ_PRIORITY         7

/*
 * MAC driver system settings.
 */
#define STM32_MAC_TRANSMIT_BUFFERS          2
#define STM32_MAC_RECEIVE_BUFFERS           4
#define STM32_MAC_BUFFERS_SIZE              1522
#define STM32_MAC_PHY_TIMEOUT               100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY         13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_ADVANCED              FALSE
#define STM32_PWM_USE_TIM1                  FALSE
#define STM32_PWM_USE_TIM2                  FALSE
#define STM32_PWM_USE_TIM3                  FALSE
#define STM32_PWM_USE_TIM4                  FALSE
#define STM32_PWM_USE_TIM5                  FALSE
#define STM32_PWM_USE_TIM8                  FALSE
#define STM32_PWM_USE_TIM9                  FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY         7
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
#define STM32_PWM_TIM5_IRQ_PRIORITY         7
#define STM32_PWM_TIM8_IRQ_PRIORITY         7
#define STM32_PWM_TIM9_IRQ_PRIORITY         7

/*
 * SDC driver system settings.
 */
#define STM32_SDC_USE_SDMMC1                TRUE
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT   TRUE
#define STM32_SDC_SDMMC_WRITE_TIMEOUT       250
#define STM32_SDC_SDMMC_READ_TIMEOUT        25
#define STM32_SDC_SDMMC_CLOCK_DELAY         10
#define STM32_SDC_SDMMC1_DMA_STREAM         STM32_DMA_STREAM_ID(2, 3)
#define STM32_SDC_SDMMC1_DMA_PRIORITY       3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY       9

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1             FALSE
#define STM32_SERIAL_USE_USART2             FALSE
#define STM32_SERIAL_USE_USART3             FALSE
#define STM32_SERIAL_USE_UART4              FALSE
#define STM32_SERIAL_USE_UART5              FALSE
#define STM32_SERIAL_USE_USART6             FALSE
#define STM32_SERIAL_USE_UART7              FALSE
#define STM32_SERIAL_USE_UART8              FALSE
#define STM32_SERIAL_USART1_PRIORITY        12
#define STM32_SERIAL_USART2_PRIORITY        12
#define STM32_SERIAL_USART3_PRIORITY        12
#define STM32_SERIAL_UART4_PRIORITY         12
#define STM32_SERIAL_UART5_PRIORITY         12
#define STM32_SERIAL_USART6_PRIORITY        12
#define STM32_SERIAL_UART7_PRIORITY         12
#define STM32_SERIAL_UART8_PRIORITY         12

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1                  FALSE
#define STM32_SPI_USE_SPI2                  FALSE
#define STM32_SPI_USE_SPI3                  FALSE
#define STM32_SPI_USE_SPI4                  FALSE
#define STM32_SPI_USE_SPI5                  FALSE
#define STM32_SPI_USE_SPI6                  FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI4_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI4_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI5_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI5_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI6_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 6)
#define STM32_SPI_SPI6_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY         1
#define STM32_SPI_SPI2_DMA_PRIORITY         1
#define STM32_SPI_SPI3_DMA_PRIORITY         1
#define STM32_SPI_SPI4_DMA_PRIORITY         1
#define STM32_SPI_SPI5_DMA_PRIORITY         1
#define STM32_SPI_SPI6_DMA_PRIORITY         1
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
#define STM32_SPI_SPI3_IRQ_PRIORITY         10
#define STM32_SPI_SPI4_IRQ_PRIORITY         10
#define STM32_SPI_SPI5_IRQ_PRIORITY         10
#define STM32_SPI_SPI6_IRQ_PRIORITY         10
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

/*
 * ST driver system settings.
 */
#define STM32_ST_IRQ_PRIORITY               8
#define STM32_ST_USE_TIMER                  2

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1               FALSE
#define STM32_UART_USE_USART2               FALSE
#define STM32_UART_USE_USART3               FALSE
#define STM32_UART_USE_UART4                FALSE
#define STM32_UART_USE_UART5                FALSE
#define STM32_UART_USE_USART6               FALSE
#define STM32_UART_USE_UART7                FALSE
#define STM32_UART_USE_UART8                FALSE
#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_UART7_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART7_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_UART8_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_UART8_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_USART1_IRQ_PRIORITY      12
#define STM32_UART_USART2_IRQ_PRIORITY      12
#define STM32_UART_USART3_IRQ_PRIORITY      12
#define STM32_UART_UART4_IRQ_PRIORITY       12
#define STM32_UART_UART5_IRQ_PRIORITY       12
#define STM32_UART_USART6_IRQ_PRIORITY      12
#define STM32_UART_USART1_DMA_PRIORITY      0
#define STM32_UART_USART2_DMA_PRIORITY      0
#define STM32_UART_USART3_DMA_PRIORITY      0
#define STM32_UART_UART4_DMA_PRIORITY       0
#define STM32_UART_UART5_DMA_PRIORITY       0
#define STM32_UART_USART6_DMA_PRIORITY      0
#define STM32_UART_UART7_DMA_PRIORITY       0
#define STM32_UART_UART8_DMA_PRIORITY       0
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

/*
 * USB driver system settings.
 */
#define STM32_USB_USE_OTG1                  FALSE
#define STM32_USB_USE_OTG2                  TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY         14
#define STM32_USB_OTG2_IRQ_PRIORITY         14
#define STM32_USB_OTG1_RX_FIFO_SIZE         512
#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE     128
#define STM32_USB_OTGFIFO_FILL_BASEPRI      0

/*
 * WDG driver system settings.
 */
#define STM32_WDG_USE_IWDG                  FALSE

#endif /* _MCUCONF_H_ */

My board.h for reference:

Code: Select all

#ifndef BOARD_H
#define BOARD_H

/*
 * Board identifier.
 */
#define BOARD_KFLY
#define BOARD_NAME                  "KFly"
#define BOARD_MAJOR_VERSION         4
#define BOARD_MINOR_VERSION         0

/*
 * Board oscillators-related settings.
 */
#if !defined(STM32_HSECLK)
#define STM32_HSECLK                25000000U
#endif

#define STM32_HSE_BYPASS

/*
 * Board voltages.
 * Required for performance limits calculation.
 */
#define STM32_VDD                   300U

/*
 * MCU type as defined in the ST header.
 */
#define STM32F746xx

/*
 * IO pins assignments.
 */
#define GPIOA_PIN0                  0U
#define GPIOA_PIN1                  1U
#define GPIOA_PIN2                  2U
#define GPIOA_PIN3                  3U
#define GPIOA_PIN4                  4U
#define GPIOA_PIN5                  5U
#define GPIOA_PIN6                  6U
#define GPIOA_PIN7                  7U
#define GPIOA_PIN8                  8U
#define GPIOA_OTG_FS_VBUS           9U
#define GPIOA_PIN10                 10U
#define GPIOA_OTG_FS_DM             11U
#define GPIOA_OTG_FS_DP             12U
#define GPIOA_SWDIO                 13U
#define GPIOA_SWCLK                 14U
#define GPIOA_PIN15                 15U

/* ... */

/*
 * IO lines assignments.
 */
#define LINE_OTG_FS_VBUS            PAL_LINE(GPIOA, 9U)
#define LINE_OTG_FS_DM              PAL_LINE(GPIOA, 11U)
#define LINE_OTG_FS_DP              PAL_LINE(GPIOA, 12U)

#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)
#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)

#define LINE_LED1                   PAL_LINE(GPIOC, 0U)
#define LINE_LED2                   PAL_LINE(GPIOC, 1U)
#define LINE_LED3                   PAL_LINE(GPIOC, 2U)

#define LINE_SD_D0                  PAL_LINE(GPIOC, 8U)
#define LINE_SD_D1                  PAL_LINE(GPIOC, 9U)
#define LINE_SD_D2                  PAL_LINE(GPIOC, 10U)
#define LINE_SD_D3                  PAL_LINE(GPIOC, 11U)
#define LINE_SD_CLK                 PAL_LINE(GPIOC, 12U)
#define LINE_SD_CMD                 PAL_LINE(GPIOD, 2U)
#define LINE_SD_DETECT              PAL_LINE(GPIOG, 13U)

#define LINE_OSC_IN                 PAL_LINE(GPIOH, 0U)
#define LINE_OSC_OUT                PAL_LINE(GPIOH, 1U)



/*
 * I/O ports initial setup, this configuration is established soon after reset
 * in the initialization code.
 * Please refer to the STM32 Reference Manual for details.
 */
#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))
#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))
#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))
#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))
#define PIN_ODR_LOW(n)              (0U << (n))
#define PIN_ODR_HIGH(n)             (1U << (n))
#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))
#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))
#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))
#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))
#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))
#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))
#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))

/*
 * GPIOA setup:
 *
 * PA11 - OTG_FS_DM                 (alternate 10).
 * PA12 - OTG_FS_DP                 (alternate 10).
 * PA13 - SWDIO                     (alternate 0).
 * PA14 - SWCLK                     (alternate 0).
 */
#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_PIN0) |             \
                                     PIN_MODE_INPUT(GPIOA_PIN1) |             \
                                     PIN_MODE_INPUT(GPIOA_PIN2) |             \
                                     PIN_MODE_INPUT(GPIOA_PIN3) |             \
                                     PIN_MODE_INPUT(GPIOA_PIN4) |             \
                                     PIN_MODE_INPUT(GPIOA_PIN5) |             \
                                     PIN_MODE_INPUT(GPIOA_PIN6) |             \
                                     PIN_MODE_INPUT(GPIOA_PIN7) |             \
                                     PIN_MODE_INPUT(GPIOA_PIN8) |             \
                                     PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) |      \
                                     PIN_MODE_INPUT(GPIOA_PIN10) |            \
                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |    \
                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |    \
                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |        \
                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |        \
                                     PIN_MODE_INPUT(GPIOA_PIN15))
#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |         \
                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |  \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |        \
                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |    \
                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |    \
                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |        \
                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |        \
                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_HIGH(GPIOA_PIN0) |            \
                                     PIN_OSPEED_HIGH(GPIOA_PIN1) |            \
                                     PIN_OSPEED_HIGH(GPIOA_PIN2) |            \
                                     PIN_OSPEED_HIGH(GPIOA_PIN3) |            \
                                     PIN_OSPEED_HIGH(GPIOA_PIN4) |            \
                                     PIN_OSPEED_HIGH(GPIOA_PIN5) |            \
                                     PIN_OSPEED_HIGH(GPIOA_PIN6) |            \
                                     PIN_OSPEED_HIGH(GPIOA_PIN7) |            \
                                     PIN_OSPEED_HIGH(GPIOA_PIN8) |            \
                                     PIN_OSPEED_HIGH(GPIOA_OTG_FS_VBUS) |     \
                                     PIN_OSPEED_HIGH(GPIOA_PIN10) |           \
                                     PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) |       \
                                     PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) |       \
                                     PIN_OSPEED_HIGH(GPIOA_SWDIO) |           \
                                     PIN_OSPEED_HIGH(GPIOA_SWCLK) |           \
                                     PIN_OSPEED_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_PUPDR             (PIN_PUPDR_PULLDOWN(GPIOA_PIN0) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN1) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN2) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN3) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN4) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN5) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN6) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN7) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN8) |         \
                                     PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |  \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN10) |        \
                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |    \
                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |    \
                                     PIN_PUPDR_PULLDOWN(GPIOA_SWDIO) |        \
                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |        \
                                     PIN_PUPDR_PULLDOWN(GPIOA_PIN15))
#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0) |               \
                                     PIN_ODR_HIGH(GPIOA_PIN1) |               \
                                     PIN_ODR_HIGH(GPIOA_PIN2) |               \
                                     PIN_ODR_HIGH(GPIOA_PIN3) |               \
                                     PIN_ODR_HIGH(GPIOA_PIN4) |               \
                                     PIN_ODR_HIGH(GPIOA_PIN5) |               \
                                     PIN_ODR_HIGH(GPIOA_PIN6) |               \
                                     PIN_ODR_HIGH(GPIOA_PIN7) |               \
                                     PIN_ODR_HIGH(GPIOA_PIN8) |               \
                                     PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) |        \
                                     PIN_ODR_HIGH(GPIOA_PIN10) |              \
                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |          \
                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |          \
                                     PIN_ODR_HIGH(GPIOA_SWDIO) |              \
                                     PIN_ODR_HIGH(GPIOA_SWCLK) |              \
                                     PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0U) |            \
                                     PIN_AFIO_AF(GPIOA_PIN1, 0U) |            \
                                     PIN_AFIO_AF(GPIOA_PIN2, 0U) |            \
                                     PIN_AFIO_AF(GPIOA_PIN3, 0U) |            \
                                     PIN_AFIO_AF(GPIOA_PIN4, 0U) |            \
                                     PIN_AFIO_AF(GPIOA_PIN5, 0U) |            \
                                     PIN_AFIO_AF(GPIOA_PIN6, 0U) |            \
                                     PIN_AFIO_AF(GPIOA_PIN7, 0U))
#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0U) |            \
                                     PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0U) |     \
                                     PIN_AFIO_AF(GPIOA_PIN10, 0U) |           \
                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) |      \
                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) |      \
                                     PIN_AFIO_AF(GPIOA_SWDIO, 0U) |           \
                                     PIN_AFIO_AF(GPIOA_SWCLK, 0U) |           \
                                     PIN_AFIO_AF(GPIOA_PIN15, 0U))

/* ... */

#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
  void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */

#endif /* BOARD_H */

Posted: **Wed Jul 27, 2016 8:26 am**

Korken wrote:On the GPIO:
I copied here as well (and have the same board configuration), the only difference is that VBUS is on a different pin and ID is not connected as I will not use HOST mode.

VBUS is a hardware signal. And there is only one pin with that function. So it needs to be on the pin where it is on the discovery board. Tough luck!

The good news is that there is a define called NO_VBUS_SENSE or something like that which will tell the USB module to allow activity even if it doesn't sense "VBUS" (= a high on that specific pin).

Posted: **Wed Jul 27, 2016 8:29 am**

Yes, try that option, forgot about that.

It is BOARD_OTG_NOVBUSSENS and is part of the board.h definitions.

Edit: Apparently it cannot be generated using the .chcfg, I need to modify the XML schema, you need to add it manually to board.h or add it to the makefile definitions.

Giovanni

Posted: **Wed Jul 27, 2016 1:36 pm**

Thanks for the tips!
Though I have it connected correctly, I am using the smaller BGA chip (201 balls vs 216 balls) compared to the DISCOVERY board, where VBUS is on PA9.
I tested with and without this command, and it made no difference.

I have also been in the electronics lab here at the university and checked for shorts / bad solder joints and it seems OK.
One thing I have discovered is that it does not seem to get D+ to go high when the pull-up should be enabled, the D+ line stays at 0V.
I have tested the lines by driving them as IOs to see that signals get through correctly, so there is no solder connection problem as well.

So, it has to be a programmatic error, just need to figure out what...

What is the difference between OTG1 and OTG2?
On my F4 version I know that OTG1 was used, but on this it is OTG2 - what is the distinction?

And is there any chance that using Chibi 16.1.x is a problem?

Thanks!

EDIT:
When adding an external 1.5k resistor the following errors are produced during enumeration:

[ 5391.053845] usb 1-2: new full-speed USB device number 17 using xhci_hcd
[ 5391.213881] usb 1-2: device descriptor read/64, error -71
[ 5391.477164] usb 1-2: device descriptor read/64, error -71
[ 5391.740442] usb 1-2: new full-speed USB device number 18 using xhci_hcd
[ 5391.900487] usb 1-2: device descriptor read/64, error -71
[ 5392.163814] usb 1-2: device descriptor read/64, error -71
[ 5392.427061] usb 1-2: new full-speed USB device number 19 using xhci_hcd
[ 5392.427294] usb 1-2: Device not responding to setup address.
[ 5392.630223] usb 1-2: Device not responding to setup address.
[ 5392.833710] usb 1-2: device not accepting address 19, error -71
[ 5392.993680] usb 1-2: new full-speed USB device number 20 using xhci_hcd
[ 5392.993949] usb 1-2: Device not responding to setup address.
[ 5393.197247] usb 1-2: Device not responding to setup address.
[ 5393.400298] usb 1-2: device not accepting address 20, error -71
[ 5393.400385] usb usb1-port2: unable to enumerate USB device

It is as if the USB is not correctly configured.

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