ChibiOS Free Embedded RTOS

Hi,

I have problems getting lwIP to work on the Nucleo 144 F207ZG.

My project is based on the demo of ST-NUCLEO144-F207ZG.

I made the following additions (beside makefile changes):
board.h
[nfo]/*
* Ethernet PHY type.
*/
#define BOARD_PHY_ID MII_LAN8742A_ID
#define BOARD_PHY_RMII

/*
* The board has an ULPI USB PHY.
*/
#define BOARD_OTG2_USES_ULPI[/nfo]

board.chcfg
[nfo]<ethernet_phy>
<identifier>MII_LAN8742A_ID</identifier>
<bus_type>RMII</bus_type>
</ethernet_phy>[/nfo]

cc.h
Added typical debug output stuff (chprintf).

I added my IP adress data in lwipthread.h.
In lwipopts I enabled ICMP, IP, UDP and enabled debug messages. I alo tryed to disabled checksums.
In main.c I initialize with lwipInit(NULL) like in the lwip examples.

But I cannot ping the board. According to the debug messages it cannot even receive a package.
Can anyone help?

The output of the startup:
[nfo]netif_set_ipaddr: netif address being changed
netif: IP address of interface set to 10.0.253.90
netif: netmask of interface set to 255.255.255.0
netif: GW address of interface set to 10.0.253.1
netif: added interface ms IP addr 10.0.253.90 netmask 255.255.255.0 gw 10.0.253.1
netif: setting default interface ms

ChibiOS/RT Shell
ch>[/nfo]

Output of thread list:
[nfo]ch> threads
stklimit stack addr refs prio state name

00000000 20000784 20006FBC 1 128 WTOREVT main
20003458 200034A4 200034E8 1 1 READY idle
200017E8 200019EC 20001AA8 1 2 WTOREVT lwipthread
200070D0 200074B4 20007550 1 3 WTSEM tcpip_thread
20001B40 20001BEC 20001C40 1 129 SLEEPING blinker
200075A0 200084B4 20008620 1 129 CURRENT shell
ch>[/nfo]


Thank you very much!

Best regards,
yarrow

Problem solved!

There were some defines (for the PHY and 3 RMII lines) missing in board.h for this board (probably for other Nucleo144 expect the F746ZG too).

Here is a patch, maybe it can be included and be useful for someone

[nfo]--- chibios-svn-9734-trunk/chibios-svn-9734-trunk/os/hal/boards/ST_NUCLEO144_F207ZG/board.h Tue Jun 28 19:13:26 2016
+++ chibios/os/hal/boards/ST_NUCLEO144_F207ZG/board.h Mon Aug 22 19:27:36 2016
@@ -32,6 +32,17 @@
#define BOARD_ST_NUCLEO144_F207ZG
#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-F207ZG"

+ /*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_LAN8742A_ID
+#define BOARD_PHY_RMII
+
+ /*
+ * The board has an ULPI USB PHY.
+ */
+#define BOARD_OTG2_USES_ULPI
+
/*
* Board oscillators-related settings.
* NOTE: LSE not fitted.
@@ -72,6 +83,7 @@
#define GPIOA_SPI1_SCK 5U
#define GPIOA_ARD_D12 6U
#define GPIOA_SPI1_MISO 6U
+#define GPIOA_RMII_CRS_DV 7U
#define GPIOA_ARD_D11 7U
#define GPIOA_SPI1_MOSI 7U
#define GPIOA_ZIO_D71 7U
@@ -109,6 +121,7 @@
#define GPIOB_TIM2_CH4 11U
#define GPIOB_ZIO_D19 12U
#define GPIOB_I2S2_WS 12U
+#define GPIOB_RMII_TXD1 13U
#define GPIOB_ZIO_D18 13U
#define GPIOB_I2S2_CK 13U
#define GPIOB_LED3 14U
@@ -225,6 +238,7 @@
#define GPIOG_ZIO_D65 0U
#define GPIOG_ZIO_D64 1U
#define GPIOG_ZIO_D49 2U
+#define GPIOG_RMII_RXER 2U
#define GPIOG_ZIO_D50 3U
#define GPIOG_PIN4 4U
#define GPIOG_PIN5 5U
@@ -324,6 +338,7 @@
#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U)
#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)
#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U)
+#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U)
#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)
#define LINE_SPI1_MOSI PAL_LINE(GPIOA, 7U)
#define LINE_ZIO_D71 PAL_LINE(GPIOA, 7U)
@@ -361,6 +376,7 @@
#define LINE_TIM2_CH4 PAL_LINE(GPIOB, 11U)
#define LINE_ZIO_D19 PAL_LINE(GPIOB, 12U)
#define LINE_I2S2_WS PAL_LINE(GPIOB, 12U)
+#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U)
#define LINE_ZIO_D18 PAL_LINE(GPIOB, 13U)
#define LINE_I2S2_CK PAL_LINE(GPIOB, 13U)
#define LINE_LED3 PAL_LINE(GPIOB, 14U)
@@ -472,6 +488,7 @@

#define LINE_ZIO_D65 PAL_LINE(GPIOG, 0U)
#define LINE_ZIO_D64 PAL_LINE(GPIOG, 1U)
+#define LINE_RMII_RXER PAL_LINE(GPIOG, 2U)
#define LINE_ZIO_D49 PAL_LINE(GPIOG, 2U)
#define LINE_ZIO_D50 PAL_LINE(GPIOG, 3U)
#define LINE_USB_GPIO_OUT PAL_LINE(GPIOG, 6U)
@@ -539,6 +556,7 @@
PIN_MODE_INPUT(GPIOA_ARD_D13) | \
PIN_MODE_INPUT(GPIOA_ARD_D12) | \
PIN_MODE_INPUT(GPIOA_ARD_D11) | \
+ PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\
PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \
PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \
PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \
@@ -555,6 +573,7 @@
PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \
PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \
PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\
PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \
PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \
PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \
@@ -573,6 +592,7 @@
PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \
PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \
PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \
+ PIN_OSPEED_VERYLOW(GPIOA_RMII_CRS_DV) |\
PIN_OSPEED_HIGH(GPIOA_USB_ID) | \
PIN_OSPEED_HIGH(GPIOA_USB_DM) | \
PIN_OSPEED_HIGH(GPIOA_USB_DP) | \
@@ -589,6 +609,7 @@
PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \
PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \
PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \
+ PIN_PUPDR_FLOATING(GPIOA_RMII_CRS_DV) |\
PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \
PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
@@ -606,6 +627,7 @@
PIN_ODR_HIGH(GPIOA_USB_SOF) | \
PIN_ODR_HIGH(GPIOA_USB_VBUS) | \
PIN_ODR_HIGH(GPIOA_USB_ID) | \
+ PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \
PIN_ODR_HIGH(GPIOA_USB_DM) | \
PIN_ODR_HIGH(GPIOA_USB_DP) | \
PIN_ODR_HIGH(GPIOA_SWDIO) | \
@@ -618,7 +640,8 @@
PIN_AFIO_AF(GPIOA_ZIO_D24, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
- PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
+ PIN_AFIO_AF(GPIOA_ARD_D11, 0U) | \
+ PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \
PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \
PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \
@@ -656,6 +679,7 @@
PIN_MODE_INPUT(GPIOB_ZIO_D22) | \
PIN_MODE_INPUT(GPIOB_ZIO_D26) | \
PIN_MODE_OUTPUT(GPIOB_LED2) | \
+ PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \
PIN_MODE_INPUT(GPIOB_ARD_D15) | \
PIN_MODE_INPUT(GPIOB_ARD_D14) | \
PIN_MODE_INPUT(GPIOB_ZIO_D36) | \
@@ -672,6 +696,7 @@
PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D22) | \
PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D26) | \
PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \
PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D36) | \
@@ -688,6 +713,7 @@
PIN_OSPEED_HIGH(GPIOB_ZIO_D22) | \
PIN_OSPEED_VERYLOW(GPIOB_ZIO_D26) | \
PIN_OSPEED_HIGH(GPIOB_LED2) | \
+ PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \
PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \
PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \
PIN_OSPEED_HIGH(GPIOB_ZIO_D36) | \
@@ -704,6 +730,7 @@
PIN_PUPDR_PULLUP(GPIOB_ZIO_D22) | \
PIN_PUPDR_PULLUP(GPIOB_ZIO_D26) | \
PIN_PUPDR_FLOATING(GPIOB_LED2) | \
+ PIN_PUPDR_FLOATING(GPIOB_RMII_TXD1) | \
PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | \
PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | \
PIN_PUPDR_PULLUP(GPIOB_ZIO_D36) | \
@@ -720,6 +747,7 @@
PIN_ODR_HIGH(GPIOB_ZIO_D22) | \
PIN_ODR_HIGH(GPIOB_ZIO_D26) | \
PIN_ODR_LOW(GPIOB_LED2) | \
+ PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \
PIN_ODR_HIGH(GPIOB_ARD_D15) | \
PIN_ODR_HIGH(GPIOB_ARD_D14) | \
PIN_ODR_HIGH(GPIOB_ZIO_D36) | \
@@ -743,6 +771,7 @@
PIN_AFIO_AF(GPIOB_ZIO_D19, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D18, 0U) | \
PIN_AFIO_AF(GPIOB_LED3, 0U) | \
+ PIN_AFIO_AF(GPIOB_RMII_TXD1, 11) | \
PIN_AFIO_AF(GPIOB_ZIO_D17, 0U))

/*
@@ -1237,6 +1266,7 @@
PIN_MODE_INPUT(GPIOG_ZIO_D64) | \
PIN_MODE_INPUT(GPIOG_ZIO_D49) | \
PIN_MODE_INPUT(GPIOG_ZIO_D50) | \
+ PIN_MODE_INPUT(GPIOG_RMII_RXER) | \
PIN_MODE_INPUT(GPIOG_PIN4) | \
PIN_MODE_INPUT(GPIOG_PIN5) | \
PIN_MODE_INPUT(GPIOG_USB_GPIO_OUT) | \
@@ -1253,6 +1283,7 @@
PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D64) | \
PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D49) | \
PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D50) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_RMII_RXER) | \
PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_OUT) |\
@@ -1269,6 +1300,7 @@
PIN_OSPEED_VERYLOW(GPIOG_ZIO_D64) | \
PIN_OSPEED_VERYLOW(GPIOG_ZIO_D49) | \
PIN_OSPEED_VERYLOW(GPIOG_ZIO_D50) | \
+ PIN_OSPEED_HIGH(GPIOG_RMII_RXER) | \
PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
PIN_OSPEED_HIGH(GPIOG_USB_GPIO_OUT) | \
@@ -1285,6 +1317,7 @@
PIN_PUPDR_PULLUP(GPIOG_ZIO_D64) | \
PIN_PUPDR_PULLUP(GPIOG_ZIO_D49) | \
PIN_PUPDR_PULLUP(GPIOG_ZIO_D50) | \
+ PIN_PUPDR_PULLUP(GPIOG_RMII_RXER) | \
PIN_PUPDR_PULLUP(GPIOG_PIN4) | \
PIN_PUPDR_PULLUP(GPIOG_PIN5) | \
PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_OUT) | \
@@ -1301,6 +1334,7 @@
PIN_ODR_HIGH(GPIOG_ZIO_D64) | \
PIN_ODR_HIGH(GPIOG_ZIO_D49) | \
PIN_ODR_HIGH(GPIOG_ZIO_D50) | \
+ PIN_ODR_HIGH(GPIOG_RMII_RXER) | \
PIN_ODR_HIGH(GPIOG_PIN4) | \
PIN_ODR_HIGH(GPIOG_PIN5) | \
PIN_ODR_HIGH(GPIOG_USB_GPIO_OUT) | \
@@ -1317,6 +1351,7 @@
PIN_AFIO_AF(GPIOG_ZIO_D64, 0U) | \
PIN_AFIO_AF(GPIOG_ZIO_D49, 0U) | \
PIN_AFIO_AF(GPIOG_ZIO_D50, 0U) | \
+ PIN_AFIO_AF(GPIOG_RMII_RXER, 0) | \
PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \[/nfo]

That board.h file is computer-generated. Not meant for humans to edit. Didn't you see the warning at the top of the file?

Yes I read the warning, but I don't use ChibiStudio so I had to change it manually. And I thought it could probably help someone.

So if the missing defines are not generated, that means there must be an error in the board.chcfg, right?
If I undestand it correctly, the board.h will be generated out of the board.chcfg, correct?

Best regards,
Yarrow

Hi,

Correct, you can use ChibiStudio also just to generate files but don't worry, we will fix it before next release.

Giovanni

Hi Giovanni,

The problem was that last time I tried ChibiStudio I needed Java x86. But for another application I needed the 64bit version. I am unsure if they can coexist on the same System. But I will give it a try

That would be great! Probably the other Nucleo144 boards are affected, too.
Thank you very much!

Best regards,
Yarrow

Hi,

They can be installed on the same system as far I know.

Giovanni

Fixed on trunk

Thanks for the fast fix!!

And yes ChibiStudio works when Java 32 and 64 is installed on the same nachine (just verified it).

Best regards,
yarrow