ChibiOS Free Embedded RTOS

This peripheral is proving to be "challenging", only after two weeks I am beginning to see some activity in the driver (reset, setup packets etc), there are a lot of small details that simply make the thing stop responding. I still don't have an ETA for this one but at least now it does something.

This thread is dedicated to this specific driver discussion.

Good to see at least something working now, keep up the good work.
Are you mainly working from the specification or from the ST supplied driver?

The specification mainly, not just the RM but also the original Synopsis document.

Giovanni

Hi Giovanni,

I've actually been struggling with this peripheral for a work project as well I was just looking through your code and saw that most things lined up with what I've been doing but saw one difference during init that was particularly tricky when I was bringing it up.

I found that if I did not initialize EP0 DIEPCTL specifically within the ENUMDNE ISR (i.e. *not* within the USBRST ISR), subsequent setup transactions could have corrupted lengths sent out on the bus - this is specified in the RM at some obscure location Not sure if this is similar to anything you've seen, but I thought I'd share it.

Also, I tried for some time to organize the driver such that I could leave OUT data in the dedicated RX fifo until the user application wanted to read it, avoiding the requirement for a dedicated buffer per endpoint, but the state machine in the HW appears to recognize an OUT transaction as complete only once that data is read out of the RX fifo. I may investigate this more in the future - would be nice to reduce the RAM requirements!

Liam

Hi Liam,

Thanks for the hint.

I am having documentation troubles too, in the ST RM manual are described registers bits that should not be present according to the Synopsis documentation, for example bits related to the "shared TX FIFO mode" but the peripheral on the STM32 is not configured with the shared TX FIFO so when you see things related to the "non periodic shared TX FIFO" or "EP mismatch interrupt" it is all stuff that shouldn't really be there.

I am still digging into the Synopsis documents but it is huge because it describes all the possible HW configurations for that peripheral, apparently some unrelated things leaked into the ST RM (and some other important info are missing...).

Giovanni