ChibiOS Free Embedded RTOS

Posted: **Fri Jan 20, 2017 6:08 pm**

Dear Giovanni,

I should write a driver to interface 24fc256 eeprom on a STM32F767 MCU. I have also got experiances and working codes with this eeprom with previous versions of ChibiOS on F4. Only the ChibiOS master branch contains support to this MCU and that is why i am using the most recent version of the master.

Code: Select all

static const I2CConfig i2cfg = {
     STM32_TIMINGR_PRESC(10U)  |
     STM32_TIMINGR_SCLDEL(9U) | STM32_TIMINGR_SDADEL(9U) |
     STM32_TIMINGR_SCLH(21U)   | STM32_TIMINGR_SCLL(24U),
    0,              // CR1
    0,              // CR2
    NULL            // Receive callback
};

uint8_t tx[2] = {0};
uint8_t buff = 0x00;

tx[0] = 0x00;   //msb addr
tx[1] = 0x00;   //lsb addr

i2cAcquireBus(&I2CD1);
i2cmsg = i2cMasterTransmitTimeout(&I2CD1, 0x50, tx, 2, &buff, 1, TIME_INFINITE);
i2cReleaseBus(&I2CD1);

I tried to read one byte from the address 0x0000 but i did not receive anything. The i2cmsg returns 0, the i2cGetErrors() returns 0. Everything seems fine. I measured the i2c bus (i attached the image) and i saw that the sent memory address is not what i expect (0x0000). I tried to modify to another address but the sent message via the i2c bus is static and doesn't react any modification.

Did i did something wrong? Do you have any idea what is the problem?

Thank you very much,
Richard

Posted: **Fri Jan 20, 2017 7:35 pm**

Hi,

Strange, addresses should work exactly like on the F4, the configuration structure is different. I assume you started the driver even if not shown in you post.

What linker file are you using? is the "tx" buffer placed in the TCM RAM? it would have cache coherency problems otherwise, because DMA does not flushes/invalidates the data cache.

Giovanni

Posted: **Sat Jan 21, 2017 12:15 am**

I have started the i2c driver. I am using the STM32F76xxI.ld script from the ChibiOS. What do you mean under TCM RAM?

Posted: **Sat Jan 21, 2017 7:32 am**

Hi,

The DTCM RAM is a dedicated high speed RAM region that does not require caching, by default C variables and buffers are placed there in ChibiOS, I imagine you are using the default .ld files so this is probably not your issue.

Just FYI, there is this article http://www.chibios.org/dokuwiki/doku.ph ... _dma_guide

Are data acknowledged by the slave? are SDA and SCL not connected to other things on the board?

Giovanni

Posted: **Sat Jan 21, 2017 9:41 am**

I have successfully used the I2C on a STM32F767 Nucleo (with a FRAM, so pretty similar to EEPROM), using the same drivers as for F0 series (F4 I2C is different).
Don't have the code to hand, but think I flushed the transmit buffer to RAM before calling the I2C routine.
Did find that I had to explicitly set the pins used to open drain - this isn't forced by selecting the alternate mode.

The F767 errata does list some problems with the I2C; not sure yet how big a problem they are.

Posted: **Sat Jan 21, 2017 11:16 am**

Hi,

I read the link you sent (http://www.chibios.org/dokuwiki/doku.ph ... _dma_guide). I followed the guide and i managed to solved the problem. Thank you very much for the help. The DMA cache coherency was the problem. Now it works fine.

Have a nice day,
Richard

ChibiOS Free Embedded RTOS

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