Page 1 of 1
Wrong PLLVCO min for STM32F415/17?
Posted: Tue Apr 18, 2017 10:49 pm
by lerela
Hi,
hal/ports/STM32/STM32F4xx/hal_lld.h defines the following:
Code: Select all
#define STM32_PLLVCO_MIN 192000000
And performs following check:
Code: Select all
#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) ...
...
#else
#error
#endif
However, reference manual page 205 says that valid values for PLLI2SN are comprised between
50 & 432. It also states that "The software has to set these bits correctly to ensure that the VCO output frequency is between
100 and 432 MHz."
Therefore it seems that STM32_PLLVCO_MIN should be 100000000 and the test should be STM32_PLLI2SN_VALUE >= 50.
I2S is working on my board with multipliers and VCO clocks that do not comply with the ChibiOS checks but with the reference manual. Those multipliers are also valid in CubeMX.
Best,
-l
Re: Wrong PLLVCO min for STM32F415/17?
Posted: Tue Apr 18, 2017 10:54 pm
by Giovanni
Hi,
Moving in bug reports.
Giovanni
Re: Wrong PLLVCO min for STM32F415/17?
Posted: Wed Apr 19, 2017 5:12 am
by RoccoMarco
I will fix this.
Re: Wrong PLLVCO min for STM32F415/17?
Posted: Sat Apr 22, 2017 2:31 pm
by RoccoMarco
Hi,
STM32F415/17 are not supported since I have no hardware to test the port. As you can see the ranges you are talking about are not for that MCU
Code: Select all
/**
* @name Absolute Maximum Ratings
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F469xx) || defined(STM32F479xx) || defined(__DOXYGEN__)
/**
* @brief Absolute maximum system clock.
*/
#define STM32_SYSCLK_MAX 180000000
/**
* @brief Maximum HSE clock frequency.
*/
#define STM32_HSECLK_MAX 26000000
/**
* @brief Maximum HSE clock frequency using an external source.
*/
#define STM32_HSECLK_BYP_MAX 50000000
/**
* @brief Minimum HSE clock frequency.
*/
#define STM32_HSECLK_MIN 4000000
/**
* @brief Minimum HSE clock frequency.
*/
#define STM32_HSECLK_BYP_MIN 1000000
/**
* @brief Maximum LSE clock frequency.
*/
#define STM32_LSECLK_MAX 32768
/**
* @brief Maximum LSE clock frequency.
*/
#define STM32_LSECLK_BYP_MAX 1000000
/**
* @brief Minimum LSE clock frequency.
*/
#define STM32_LSECLK_MIN 32768
/**
* @brief Maximum PLLs input clock frequency.
*/
#define STM32_PLLIN_MAX 2100000
/**
* @brief Minimum PLLs input clock frequency.
*/
#define STM32_PLLIN_MIN 950000
/**
* @brief Maximum PLLs VCO clock frequency.
*/
#define STM32_PLLVCO_MAX 432000000
/**
* @brief Minimum PLLs VCO clock frequency.
*/
#define STM32_PLLVCO_MIN 192000000
/**
* @brief Maximum PLL output clock frequency.
*/
#define STM32_PLLOUT_MAX 180000000
/**
* @brief Minimum PLL output clock frequency.
*/
#define STM32_PLLOUT_MIN 24000000
/**
* @brief Maximum PLLI2S output clock frequency.
*/
#define STM32_PLLI2SOUT_MAX 216000000
/**
* @brief Maximum PLLSAI output clock frequency.
*/
#define STM32_PLLSAIOUT_MAX 216000000
/**
* @brief Maximum APB1 clock frequency.
*/
#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
/**
* @brief Maximum APB2 clock frequency.
*/
#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
/**
* @brief Maximum SPI/I2S clock frequency.
*/
#define STM32_SPII2S_MAX 45000000
#endif
#if defined(STM32F40_41xxx)
#define STM32_SYSCLK_MAX 168000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
#define STM32_HSECLK_MIN 4000000
#define STM32_HSECLK_BYP_MIN 1000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
#define STM32_LSECLK_MIN 32768
#define STM32_PLLIN_MAX 2100000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
#define STM32_PLLVCO_MIN 192000000
#define STM32_PLLOUT_MAX 168000000
#define STM32_PLLOUT_MIN 24000000
#define STM32_PCLK1_MAX 42000000
#define STM32_PCLK2_MAX 84000000
#define STM32_SPII2S_MAX 42000000
#endif
#if defined(STM32F401xx)
#define STM32_SYSCLK_MAX 84000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
#define STM32_HSECLK_MIN 4000000
#define STM32_HSECLK_BYP_MIN 1000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
#define STM32_LSECLK_MIN 32768
#define STM32_PLLIN_MAX 2100000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
#define STM32_PLLVCO_MIN 192000000
#define STM32_PLLOUT_MAX 84000000
#define STM32_PLLOUT_MIN 24000000
#define STM32_PCLK1_MAX 42000000
#define STM32_PCLK2_MAX 84000000
#define STM32_SPII2S_MAX 42000000
#endif
#if defined(STM32F410xx) || defined(STM32F411xx) || \
defined(STM32F412xx)
#define STM32_SYSCLK_MAX 100000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
#define STM32_HSECLK_MIN 4000000
#define STM32_HSECLK_BYP_MIN 1000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
#define STM32_LSECLK_MIN 32768
#define STM32_PLLIN_MAX 2100000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
#define STM32_PLLVCO_MIN 100000000
#define STM32_PLLOUT_MAX 100000000
#define STM32_PLLOUT_MIN 24000000
#define STM32_PCLK1_MAX 50000000
#define STM32_PCLK2_MAX 100000000
#define STM32_SPII2S_MAX 50000000
#endif
#if defined(STM32F446xx)
#define STM32_SYSCLK_MAX 180000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 50000000
#define STM32_HSECLK_MIN 4000000
#define STM32_HSECLK_BYP_MIN 1000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
#define STM32_LSECLK_MIN 32768
#define STM32_PLLIN_MAX 2100000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
#define STM32_PLLVCO_MIN 100000000
#define STM32_PLLOUT_MAX 180000000
#define STM32_PLLOUT_MIN 12500000
#define STM32_PLLI2SOUT_MAX 216000000
#define STM32_PLLSAIOUT_MAX 216000000
#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
#define STM32_SPII2S_MAX 45000000
#endif
#if defined(STM32F2XX)
#define STM32_SYSCLK_MAX 120000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 26000000
#define STM32_HSECLK_MIN 1000000
#define STM32_HSECLK_BYP_MIN 1000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
#define STM32_LSECLK_MIN 32768
#define STM32_PLLIN_MAX 2000000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
#define STM32_PLLVCO_MIN 192000000
#define STM32_PLLOUT_MAX 120000000
#define STM32_PLLOUT_MIN 24000000
#define STM32_PCLK1_MAX 30000000
#define STM32_PCLK2_MAX 60000000
#define STM32_SPII2S_MAX 30000000
#endif
/** @} */
There are any nucleo or discovery with that MCU?
Re: Wrong PLLVCO min for STM32F415/17?
Posted: Tue May 02, 2017 9:52 pm
by lerela
Hi RM,
Sorry for the late answer. You're talking about line 179, I'm talking about line 219.
I believe it is for this MCU (and it does fix the problem at compilation time):
Code: Select all
#if defined(STM32F40_41xxx) || defined(__DOXYGEN__)
Here is the patch:
Code: Select all
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index 877f756..2e06438 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -216,7 +216,7 @@
#define STM32_PLLIN_MAX 2100000
#define STM32_PLLIN_MIN 950000
#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 192000000
+#define STM32_PLLVCO_MIN 100000000
#define STM32_PLLOUT_MAX 168000000
#define STM32_PLLOUT_MIN 24000000
#define STM32_PCLK1_MAX 42000000
@@ -1289,7 +1289,7 @@
/**
* @brief STM32_PLLI2SN field.
*/
-#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \
+#if ((STM32_PLLI2SN_VALUE >= 100) && (STM32_PLLI2SN_VALUE <= 432)) || \
defined(__DOXYGEN__)
#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
#else
There's a DK for the 413 which should have the same behavior (32F413HDISCOVERY).
Best,
-l
Re: Wrong PLLVCO min for STM32F415/17?
Posted: Tue May 02, 2017 10:10 pm
by RoccoMarco
I will take a look to the code. I have a F412discovery but I have noticed that there is a detail in a register which requires a split in hal lld files.
I will add support for this MCU right after the next major release which should be imminent.
Right now I will just add these defines of maximum absolute ratings.