Fast Interrupt Jitter
Posted: Wed Sep 20, 2017 12:32 pm
Hi everyone,
we have a problem with fast interrupts which we have not been able to solve for a while. It may not be directly related to chibios, but I still think this is the best place to ask.
We are using the internal comparator (COMP1) on the F3-series to generate a fast interrupt. These interrupts are generated via the exti-system (line 21), everything is configured accordingly, without using the OS functions. The vector was added to vectors.c and triggers reliably, the routine right now does almost nothing except clear interrupt and flag, check for the comp state and switch a GPIO-pin.
The problem is the jitter we are seeing, the time between an edge on the external comparator signal and the GPIO edge varies between 300 and 1050 ns, at 72MHz this is 20-75 cycles. For our application a constant value as low as possible is important (300ns would be great), so we tried everything but we can not get rid of the jitter. I was expecting the jitter to be much lower for a fast interrupt without OS interaction. Does anyone have any experience whether this amount of jitter is normal? Any idea how to reduce it?
We would be gerateful for any help. The code of configuration and ISR routine is below.
Best regards,
Thomas
Configuration:
Interrupt routine:
we have a problem with fast interrupts which we have not been able to solve for a while. It may not be directly related to chibios, but I still think this is the best place to ask.
We are using the internal comparator (COMP1) on the F3-series to generate a fast interrupt. These interrupts are generated via the exti-system (line 21), everything is configured accordingly, without using the OS functions. The vector was added to vectors.c and triggers reliably, the routine right now does almost nothing except clear interrupt and flag, check for the comp state and switch a GPIO-pin.
The problem is the jitter we are seeing, the time between an edge on the external comparator signal and the GPIO edge varies between 300 and 1050 ns, at 72MHz this is 20-75 cycles. For our application a constant value as low as possible is important (300ns would be great), so we tried everything but we can not get rid of the jitter. I was expecting the jitter to be much lower for a fast interrupt without OS interaction. Does anyone have any experience whether this amount of jitter is normal? Any idea how to reduce it?
We would be gerateful for any help. The code of configuration and ISR routine is below.
Best regards,
Thomas
Configuration:
Code: Select all
EXTI->IMR |= EXTI_IMR_MR21; //enable EXTI for comparator output
EXTI->RTSR |= EXTI_RTSR_TR21; //Detect rising edge at comparator output
EXTI->FTSR |= EXTI_FTSR_TR21; //Detect falling edge at comparator output
nvicEnableVector(COMP1_2_3_IRQn,0); // enable interrupt with high priorityInterrupt routine:
Code: Select all
CH_FAST_IRQ_HANDLER(Vector140)
{
nvicClearPending(COMP1_2_3_IRQn);
EXTI->PR &= ~EXTI_PR_PR21; // clear flag of comp interrupt
if ((COMP->CSR & COMP1_CSR_COMP1OUT))
{
palSetPad(GPIOA, GPIOA_MCU_OUT); //Turn gate off
}
else
{
palClearPad(GPIOA, GPIOA_MCU_OUT); //Turn gate on
}
}