ChibiOS Free Embedded RTOS

Posted: **Sun Mar 17, 2019 9:17 am**

Hi,

Putting this here to keep track.

Several LLDs have DMA-accessible buffers inside the driver structure, this is a problem on those devices where cache coherency must be handled.

Required action: move all buffers outside the driver structure, replace those with a pointer to the actual buffer which should be aligned to cache lines.

Giovanni

Posted: **Sun Nov 10, 2019 10:22 am**

Posted: **Mon Mar 17, 2025 1:55 pm**

Has this been addressed? If so, in what versions?

Posted: **Mon Mar 17, 2025 2:54 pm**

This has been addressed for SNOR, now XSNOR. I need to check sd_mmc but I think it was addressed there too.

Giovanni

Posted: **Tue Mar 18, 2025 2:16 am**

Addressed the SPI dummy variables as well by allowing the entire driver structure to be located in non-cache.
Drivers now have this for allocation...

Code: Select all

/** @brief SPI1 driver identifier.*/
#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
SPI_SPID1_MEMORY SPIDriver SPID1;
#endif

So just define the non-cache section to be used.

ChibiOS Free Embedded RTOS

Cache-related problem in some STM32 HAL drivers

Cache-related problem in some STM32 HAL drivers

Re: Cache-related problem in some STM32 HAL drivers

Re: Cache-related problem in some STM32 HAL drivers

Re: Cache-related problem in some STM32 HAL drivers

Re: Cache-related problem in some STM32 HAL drivers