In ChibiOS/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h specified such defines
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#define ADC_SMPR_SMP_1P5 0U /**< @brief 14 cycles conversion time */
#define ADC_SMPR_SMP_7P5 1U /**< @brief 21 cycles conversion time. */
#define ADC_SMPR_SMP_13P5 2U /**< @brief 28 cycles conversion time. */
#define ADC_SMPR_SMP_28P5 3U /**< @brief 41 cycles conversion time. */
#define ADC_SMPR_SMP_41P5 4U /**< @brief 54 cycles conversion time. */
#define ADC_SMPR_SMP_55P5 5U /**< @brief 68 cycles conversion time. */
#define ADC_SMPR_SMP_71P5 6U /**< @brief 84 cycles conversion time. */
#define ADC_SMPR_SMP_239P5 7U /**< @brief 252 cycles conversion time. */
But in stm32L031 LL (Law layer driver) specified such defines
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#define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP_0) /*!< Sampling time 3.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_1) /*!< Sampling time 7.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 12.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP_2) /*!< Sampling time 19.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0) /*!< Sampling time 39.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1) /*!< Sampling time 79.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 160.5 ADC clock cycles */What difines is correct?
