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Bit missing for STM32L476 ?

Posted: Mon Mar 30, 2020 1:33 pm
by Stephane
Hello,

Not sure, but it seems that the LPUART1_CR3, bit UCESM is missing.

Perhaps must he be in C:\ChibiStudio\chibios191\os\common\ext\ST\STM32L4xx\stm32l476xx

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#define USART_CR3_UCESM_Pos           (23U)
#define USART_CR3_UCESM_Msk           (0x1U << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable inStop Mode */


Ah, and also for the UARTs: the TCBGTIE bit ia also missing:

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#define USART_CR3_TCBGTIE_Pos           (24U)
#define USART_CR3_TCBGTIE_Msk           (0x1U << USART_CR3_TCBGTIE_Pos)            /*!< 0x01000000 */
#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                      /*!< Trm complete before guard time IRQ enable */


With best regards,

Stephane

Re: Bit missing for STM32L476 ?

Posted: Sat May 23, 2020 9:06 am
by Giovanni
Hi,

That is an ST header, I will look for an updated version.

Giovanni

Re: Bit missing for STM32L476 ?

Posted: Sun May 31, 2020 8:59 am
by Giovanni
Hi,

I updated the headers in trunk, they added UCESM but not the other one...

Giovanni

Re: Bit missing for STM32L476 ?

Posted: Mon Jun 08, 2020 4:22 pm
by rew
That UESM / UECSM bit seems troublesome... Found this in the code I'm working on.

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  // Bit 1 is called UESM, and documented as "reserved".... Quite
  // possible that it DOES do something. ... Update: documentation
  // error. bit not implemented.

The "not implemented" remark refers to STM32F030.

Re: Bit missing for STM32L476 ?

Posted: Mon Jun 08, 2020 5:38 pm
by Giovanni
It is also possible it has been removed from documentation because some underlying problem in that feature, I don't know but it can happen.

Giovanni

Re: Bit missing for STM32L476 ?

Posted: Wed Jun 10, 2020 6:03 am
by rew
Yeah, but then the bit in the register would physically exist, just not do precisely what it's supposed to do. In this case, I tested it and found the bit completely absent in the hardware.