ChibiOS Free Embedded RTOS

While doing some direct DMA programming on an STM32L476, I made the mistake of setting the DMA IRQ priority to zero. As a result, when my program made heavy use of the USART, the USART ISR would be interrupted by a DMA interrupt while running inside of the chSysLockFromISR() protected zone, triggering an assertion halt (blessed ChibiOS checks).

Before I realized where the real problem was, setting CORTEX_SIMPLIFIED_PRIORITY to TRUE would fix the problem, which kind of lead me to the actual cause.

As far as I understand, the problem is that when CORTEX_SIMPLIFIED_PRIORITY is FALSE, chSysLockFromISR() will just raise the allowed interrupt to “kernel level” (“svc #0 in chcoreasm_v7m.S), so setting any interrupt level to 0 will cause the interrupt to be serviced even after calling chSysLockFromISR().

So I tried to set DMA IRQ priority to 1… and the problem persisted. Setting the priority to 2 fixes the problem, and in fact the lowerst IRQ priority I have ever seen in mcuconf.h is 2.

Question: why does priority 1 not fix the problem?

I guess this is actually a question about ChibiOS internals.

Also it would be nice to have an assertion triggered if attempting to set an IRQ priority lower than... 2?

Hi,

Priorities 0 and 1 are reserved, those are the highest priorities, not the lowest. IRQ at those priorities can preempt the kernel so must never use any OS call or macro. Simplified priorities have no reserved levels.

Giovanni

May I suggest to add an assertion in the code?

ChibiOS checks and assertions are a blessing, and that one would have saved quite a bit of time.

HAL already does not allow to set invalid priorities.

Manually setting priorities using NVIC API is not an error, priorities 0 and 1 are meant to be used as fast interrupts.

Giovanni

Giovanni wrote:HAL already does not allow to set invalid priorities.

Manually setting priorities using NVIC API is not an error, priorities 0 and 1 are meant to be used as fast interrupts.

Giovanni

The DMA HAL does indeed allow to set invalid priorities 0 and 1.