Cortex-M7: DTCM-RAM Section In Linker File
Posted: Mon Jun 15, 2020 4:43 am
Hello,
In the STM32F743 example in v19.1.3 of ChibiOS, vectors.S, the first address placed in the .vectors section is __main_stack_end__, followed by Reset_Handler. Why is that?
Looking at the NVIC table in the reference manual, it has the first vector with an address offset of 0x00000000 labeled as "RESERVED", followed by the Reset vector. I understand that the Main stack is responsible for handling interrupts and exceptions, but the only thing I can find related to this is in the programming manual for Cortex-M7 where it states:
Thank you.
In the STM32F743 example in v19.1.3 of ChibiOS, vectors.S, the first address placed in the .vectors section is __main_stack_end__, followed by Reset_Handler. Why is that?
Looking at the NVIC table in the reference manual, it has the first vector with an address offset of 0x00000000 labeled as "RESERVED", followed by the Reset vector. I understand that the Main stack is responsible for handling interrupts and exceptions, but the only thing I can find related to this is in the programming manual for Cortex-M7 where it states:
However address 0x00000000 is the starting address in the ITCM-RAM section. It doesn't look like the ITCM-RAM section is being utilized in the demo project though.On reset, the processor loads the MSP with the value from address 0x00000000.
Thank you.