nvicSetSystemHandlerPriority writes to wrong SHP register on Cortex-M0+/M0/M23
Posted: Fri Jun 12, 2026 10:35 am
Hi,
function nvicSetSystemHandlerPriority uses handler (e.g., HANDLER_SYSTICK = 11) directly with the CMSIS macros _SHP_IDX() and _BIT_SHIFT(). These macros expect the negative system exception number (e.g., SysTick_IRQn = -1), not the positive handler index. This results in an incorrect byte offset in the SCB->SHP array, leaving the intended handler priority unchanged and potentially corrupting another handler’s priority.
Suggested fix:
int32_t irqn = (int32_t)handler - 12;
SCB->__SHPR[_SHP_IDX(irqn)] = (SCB->__SHPR[_SHP_IDX(irqn)] & ~(0xFFU << _BIT_SHIFT(irqn))) |
(NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(irqn));
function nvicSetSystemHandlerPriority uses handler (e.g., HANDLER_SYSTICK = 11) directly with the CMSIS macros _SHP_IDX() and _BIT_SHIFT(). These macros expect the negative system exception number (e.g., SysTick_IRQn = -1), not the positive handler index. This results in an incorrect byte offset in the SCB->SHP array, leaving the intended handler priority unchanged and potentially corrupting another handler’s priority.
Suggested fix:
int32_t irqn = (int32_t)handler - 12;
SCB->__SHPR[_SHP_IDX(irqn)] = (SCB->__SHPR[_SHP_IDX(irqn)] & ~(0xFFU << _BIT_SHIFT(irqn))) |
(NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(irqn));