Hello,
I have taken the QSPI-N25Q128 example project from the STM32L4xx and changed it so it works for the STM32F746-DISCO platform.
For now the pins are set manually in the main file, but I also attached a changed board.h file for the STM32F746-DISCO. If that board file is used then the pin ...
Search found 7 matches
- Thu Jun 15, 2017 8:11 pm
- Forum: User Projects
- Topic: m25q STM32F746-DISCO example project (QSPI-N25Q128)
- Replies: 0
- Views: 4133
- Thu Jun 15, 2017 8:08 pm
- Forum: Bug Reports
- Topic: Cortex-M7 m25q-driver cache coherency
- Replies: 3
- Views: 5075
Cortex-M7 m25q-driver cache coherency
Hello again,
Here I am with another cache coherency problem on the M7-platform.
The m25q-driver in the ChibiOS trunk utilizes QSPI. The problem is that DMA is used for the transfer and of course on the M7-platform the cache coherency problem pops up again . The mayor problem I had was:
- The ...
Here I am with another cache coherency problem on the M7-platform.
The m25q-driver in the ChibiOS trunk utilizes QSPI. The problem is that DMA is used for the transfer and of course on the M7-platform the cache coherency problem pops up again . The mayor problem I had was:
- The ...
- Tue May 30, 2017 6:40 pm
- Forum: Bug Reports
- Topic: STM32F746-DISCO FMC/LTDC pin configurations
- Replies: 3
- Views: 5343
Re: STM32F746-DISCO FMC/LTDC pin configurations
That is very good news!
Thanks for committing the fix!
Thanks for committing the fix!
- Tue May 23, 2017 8:46 pm
- Forum: Bug Reports
- Topic: Cortex-M7 platform FatFS Cache coherency
- Replies: 6
- Views: 9989
Cortex-M7 platform FatFS Cache coherency
Hello,
- So after running into problems with the M7 cache coherency and my SPI driver ( thanks to Giovanni for helping me with that!) I also found that the same problems occur when using the FatFS libary on the M7-platform.
- Currently I am using ChibiOS_16.1.8
- Compiled with gcc-arm-none-eabi-5_4 ...
- So after running into problems with the M7 cache coherency and my SPI driver ( thanks to Giovanni for helping me with that!) I also found that the same problems occur when using the FatFS libary on the M7-platform.
- Currently I am using ChibiOS_16.1.8
- Compiled with gcc-arm-none-eabi-5_4 ...
- Mon May 22, 2017 2:26 pm
- Forum: STM32 Support
- Topic: STM32F746-DISCO heap problems
- Replies: 3
- Views: 4690
Re: STM32F746-DISCO heap problems
That is exactly what was happening! Quickly tested the buffer flushing and invalidation and that works perfectly.
I did not know cache coherency was a problem on the F7 platform. Good to know!
Thanks a lot for the help!
I did not know cache coherency was a problem on the F7 platform. Good to know!
Thanks a lot for the help!
- Mon May 22, 2017 12:27 pm
- Forum: STM32 Support
- Topic: STM32F746-DISCO heap problems
- Replies: 3
- Views: 4690
STM32F746-DISCO heap problems
Hello,
I am developing an application an the STM32F746-discovery board with ChibiOS. Now I am having trouble with the heap memory.
When setting the CH_CFG_MEMCORE_SIZE to zero to let ChibiOS manage all the available RAM, the '__heap_base__' is set to 0x2001 0080 and '__heap_end__' is set to 0x2005 ...
I am developing an application an the STM32F746-discovery board with ChibiOS. Now I am having trouble with the heap memory.
When setting the CH_CFG_MEMCORE_SIZE to zero to let ChibiOS manage all the available RAM, the '__heap_base__' is set to 0x2001 0080 and '__heap_end__' is set to 0x2005 ...
- Fri Apr 28, 2017 5:10 pm
- Forum: Bug Reports
- Topic: STM32F746-DISCO FMC/LTDC pin configurations
- Replies: 3
- Views: 5343
STM32F746-DISCO FMC/LTDC pin configurations
Hello,
- I have been debugging the problems that occurred while using uGFX together with ChibiOS on the STM32F746-DISCO platform.
After allot of searching I have come to the conclusion that the problem is located in the pin configurations. Two pins are configured differently than expected.
- This is ...
- I have been debugging the problems that occurred while using uGFX together with ChibiOS on the STM32F746-DISCO platform.
After allot of searching I have come to the conclusion that the problem is located in the pin configurations. Two pins are configured differently than expected.
- This is ...