sdc_lld_write_aligned() logic is correct as it is. which is:
1- host prepares data.
2- send command to peripheral to be ready to receive data.
3- enable dma to start transfer.
in fact if we change the sequence 2 and 3 it will result in data loss at peripheral end.
correct read sequence:
1- host ...
Search found 3 matches
- Wed Jan 22, 2014 6:18 am
- Forum: STM32 Support
- Topic: [DONE] Issue with SDIO Hal(for STM32) in chibios 2.6.1
- Replies: 6
- Views: 7447
- Thu Dec 05, 2013 5:45 am
- Forum: STM32 Support
- Topic: [DONE] Issue with SDIO Hal(for STM32) in chibios 2.6.1
- Replies: 6
- Views: 7447
[DONE] Issue with SDIO Hal(for STM32) in chibios 2.6.1
While working on a custom STM32F4 based board we encountered some issues with timings in SDIO HAL. SDIO is used in IO mode so small changes were required to enable CMD52 and 53. Everything seemed to work fine at low SDIO clock settings (up to 3MHz) but at higher clocks SDIO Controller started ...
- Tue Aug 27, 2013 6:09 am
- Forum: STM32 Support
- Topic: Configuring STM3210C-EVAL with the lwip example
- Replies: 22
- Views: 17820
Re: Configuring STM3210C-EVAL with the lwip example
what is the status of your problem now?
I faced the same issue with stm32f4-eval board and after lots of tries i finally got it working. If you tell me exactly where are you stuck i might be able to help.
as a starting point take the board files from the following link and check the ethernet pin ...
I faced the same issue with stm32f4-eval board and after lots of tries i finally got it working. If you tell me exactly where are you stuck i might be able to help.
as a starting point take the board files from the following link and check the ethernet pin ...