[DONE] The New STM32F429/F439
- Giovanni
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trepidacious
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Re: [TODO] The New STM32F429/F439
I've tried with Texane stlink (it seems to have added support for 42X in current git), and it seems happy to flash and debug. I get the same result as Tectu, hanging on:
The interesting thing is that the very first time I flashed the board, it did blink the red and green LEDs, until I reset the board and it stopped, now it always seems to hang, not sure what would cause that.
Code: Select all
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)The interesting thing is that the very first time I flashed the board, it did blink the red and green LEDs, until I reset the board and it stopped, now it always seems to hang, not sure what would cause that.
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Re: [TODO] The New STM32F429/F439
It is like it retained some setting from the previous code in Flash, then, after reset it started to malfunction. There must be a difference around VOS handling, good hint.
Giovanni
Giovanni
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trepidacious
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Re: [TODO] The New STM32F429/F439
Yes I think so - VOS was one of the things I noticed has changed, it now has another bit (1:0 rather than just 0), I think setting this one to 0 gets you Scale 3, which seems to only work for 120MHz? I'll try setting some different bits 
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Re: [TODO] The New STM32F429/F439
May be I found the root cause, from the RM:
Apparently, unlike the older F40x, the VOS switch is performed after activating the PLL, so the wait loop should be moved after the PLL activation. As soon I am able to flash the device I will test this hypothesis, could somebody give it a try?
Giovanni
memories and digital peripherals). In this mode, the regulator output voltage (around
1.2 V) can be scaled by software to different voltage values (scale 1, scale 2, and scale
3 can be configured through VOS[1:0] bits of the PWR_CR register). The scale can be
modified only when the PLL is OFF and the HSI or HSE clock source is selected as
system clock source. The new value programmed is active only when the PLL is ON.
When the PLL is OFF, the voltage scale 3 is automatically selected.
The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency. After exit from Stop mode, the voltage
Apparently, unlike the older F40x, the VOS switch is performed after activating the PLL, so the wait loop should be moved after the PLL activation. As soon I am able to flash the device I will test this hypothesis, could somebody give it a try?
Giovanni
- Giovanni
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Re: [TODO] The New STM32F429/F439
Fixed, it works 
OpenOCD works too... I was using the version 0.6.0... 0.7.0 is fine using the target stm32f4_stlink.cfg.
The demo does not yet initialize the SDRAM and the LCD.
Giovanni
OpenOCD works too... I was using the version 0.6.0... 0.7.0 is fine using the target stm32f4_stlink.cfg.
The demo does not yet initialize the SDRAM and the LCD.
Giovanni
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trepidacious
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Re: [TODO] The New STM32F429/F439
Too late to be useful, but I tried the change and it works
I had a USB problem but I that might just be me not plugging the cable in, doh 
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trepidacious
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Re: [TODO] The New STM32F429/F439
I still seem to get a hang at:
If I remove the USB serial code it runs the blink threads fine.
Code: Select all
0x080071aa in otg_core_reset (usbp=0x20001148 <USBD2>)
at ../../os/hal/platforms/STM32/OTGv1/usb_lld.c:133
133 while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
If I remove the USB serial code it runs the blink threads fine.
- Giovanni
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Re: [TODO] The New STM32F429/F439
Strange, the USB is working for me. Can somebody else confirm?
Giovanni
Giovanni
Re: [TODO] The New STM32F429/F439
I sadly have to stick to trepidacious... It keeps hanging here for me as well:
~ Tectu
Code: Select all
0x080075ea in otg_core_reset (usbp=0x20001148) at ../../os/hal/platforms/STM32/OTGv1/usb_lld.c:133
133 while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
~ Tectu