STM32F4Discovery low power consumption

[stylon]

Hi all,

I've developed some code for the STM32F4 on the Discovery and before starting on my own hardware design I'd like to trim the code for minimal power consumption. I already played around with different values for STM32_HPRE and STM32_PPRE1, but obviously I can't go below STM32_PPRE1 == STM32_PPRE1_DIV1. So far, the lowest setting I can use without losing the peripherals (even GPIO) is 168/4 = 42 MHz (STM32_HPRE = STM32_HPRE_DIV4, STM32_PPRE1 = STM32_PPRE1_DIV1). According to the STM32F417 manual, the power consumption should be between 16mA (30MHz) and 30mA (60MHz) in that configuration and it actually reads at 23mA for me (good, I would say). However, when I try to tune it down further (STM32_HPRE > DIV4), I'm losing the peripherals somehow, so I can't even check via GPIO and blinking LEDs wether the CPU is still running, and I also don't see the power consumption to drop according to the user manual. So, 2 questions:

• Does anyone have experience with running ChibiOS on the STM32F4 at clock frequencies < 42MHz and if yes, can you please share?
• I guess that while trying to set the clock frequency below 42MHz, I actually locked the CPU somehow, so it's not able to execute any GPIO pull up/down code for proper termination. That would explain why I don't see lower power consumption below <42MHz. Maybe someone can confirm that what I tried will lock the CPU?

I can try to isolate some of the setup code and post it here.

Best,
STYLON

[Giovanni]

Hi,

It is very simple: You can run it from the external crystal bypassing the PLL. The settings are in mcuconf.h, a good read of the clock three in the RM is recommended.

Giovanni

[stylon]

It is very simple: You can run it from the external crystal bypassing the PLL. The settings are in mcuconf.h, a good read of the clock three in the RM is recommended.

I knew the clock tree, but didn't realize that for the current consumption measurements ST only used the PLL for clock frequencies >25MHz, so below they varied external crystals. Thanks for the hint. I got their numbers in part verified now. I also got the power consumption verified using WFI in ChibiOS's idle thread (#define CORTEX_ENABLE_WFI_IDLE TRUE).

However, my particular interest was more on how to set up the clock for the peripherals (that's why I was talking about the clock dividers and not the PLL) and how (well) does it work in combination with ChibiOS? Keeping the PLL locked it seems as if I can only scale down the CPU clock by a max. factor of 4 (HPRE, and inversely decrease PPRE1). In order to go for more I need to set up all my peripherals again as the master clock changes. Something that also puzzles me: the clock setup is controlled by mcuconf.h, so, what's the best way to switch between PLL, HSE and HSI clock sources from runtime code?

Best,
STYLON

[Giovanni]

Hi,

The HAL is not designed to allow dynamic switching of those parameters because I am not sure the STM32 copes with that nicely, barthess created a dynamic variant a while ago but I don't know the current status.

HAL for SPC5xx for example supports dynamic switching but because there is HW support for it.

Note that playing with the AHB prescaler and the APB prescalers you could do some dynamic changes. It is possible to divide the PLL clock up to 512.
Playing with both you may keep the peripherals working at the same frequency while clocking up/down the CPU.

For example, writing in RCC_CFGR:
Default setting for max performance: HPRE=1, PPREx=16
Default setting for low performance: HPRE=8, PPREx=2
The total division value does not change from peripherals perspective so settings should be the same.

Note that during switch the clock behavior could be "strange" for some peripherals. I would stop drivers and start them again after switching and waiting some milliseconds.

What IS affected is system tick, it is 8 times slower in low performance mode. Note that some peripherals are affected by the AHB frequency: OTG for sure, so verify the RM.

Giovanni

[kenyee]

the power consumption should be between 16mA (30MHz) and 30mA (60MHz) in that configuration and it actually reads at 23mA for me

You're getting this value by measuring how much the entire board consumes while running at slowest speed? That's not bad at all. When I worked on a project w/ the Atmel AT91, this was called "slug mode"...but I think they brought it down to 8MHz because the chip supported it (it didn't have as high a max speed as the STM32F4).