[DONE] STM32F30x advanced timer center aligned PWM

[tecnologic]

Hi everybody,

i have 2 questions about the advanced timers of the STM32F3.

first: how du i correctly setup the 144MHz Timer Clock with the STM running on 72MHz. The 2.6.x implementation in pwm_lld.c uses
STM32_TIMCLK2 define as Clock for the Timer.

but this code from hal_lld.h for STM32F30x says:

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/**
 * @brief   TIM1 frequency.
 */
#if STM32_TIM1SW == STM32_TIM1SW_PCLK2
#define STM32_TIM1CLK               STM32_PCLK2
#elif STM32_TIM1SW == STM32_TIM1SW_PLLX2
#define STM32_TIM1CLK               (STM32_PLLCLKOUT * 2)
#else
#error "invalid source selected for TIM1 clock"
#endif

If i set STM32_TIM1SW_PLLX2 in mcuconf as timer 1 clock source i get 144MHz.
So do i have a bug here that line 413 in pwm_lld.c which is:

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pwmp->clock = STM32_TIMCLK2;

should be

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pwmp->clock = STM32_TIM1CLK;

and so for TIM8 as well.

So how can i get 144MHz base clock for my PWM on TIM1.

my second question is: how is center aligned pwm correctly configured with the pwm driver? normaly the PWM driver uses PWM Mode 1.
I need this mode for my 3 phase pwm to save switching losses and being able to sample the ADC in the middle of the high time of the dutycycle.

If this mode is not implemented jet i would write a patch using a define like STM32_PWM_USE_CENTER_ALIGNED to activate this mode.

Thanks

Tec

[Giovanni]

I am looking into the clock issue, the center aligned mode has been implemented in the SPC5xx PWM driver, you may use similar definitions for the STM32 version.

Giovanni

[tecnologic]

Hi Giovanni,

i made a test where i activated the STM32_TIM_CR1_CMS(1) bits. i hade issues with channel 3 which would not work correctly complementary, i think i missd something. My STM Lib code works correctly i will check that.

For the center aligned patch i thought of adding CR1 and to the PWMConfig. which could be ored to the actual CR1 Register value. So we are most flexible. And i'll add the defines from SPC5 driver. my be i'll get it working this year.

Greets

Tec

[Giovanni]

Just a note, if the required changes break the compatibility then the work should be finalized to the version 3.0 because 2.6.x is supposed to be stable.

Giovanni

[Giovanni]

Fixed the clock issue as bug #448. Changes were required also in the GPT and ICU drivers.

Could you give the fix a try?

Giovanni

[tecnologic]

Hi Giovanni.

i'll pull the change. and try it. but to verify für freqency i need too be back at my lab, in für beginning next year.

to 3.0. i would Mike do usw 3.0 which Branch can i use? due to the fact that my project uses c++ i need für c++ wrapper. but in für 3.0 i tryed it was completly un ported. so i was careful. i have no problem porting c++ layer and motion control relevant hal components for stm32f30x. cause i want to use this for my master thesis. but i will need some guidiance according API decisions.

greets

Tec

[Giovanni]

Hi,

I cannot yet freeze the 3.0 API, I will try to port the current wrapper but changes are not impossible until it is released. Of course you may create a temporary wrapper for your work, the API is not that different after all.

Giovanni

[tecnologic]

HI,

the clock fix seams to work, i could not measure till next year, but init with 144MHz works and macros seem to be logic.

but i yust found a other bug .

In stm32_tim.h in line 183 there is the right shift by 2 for the fouth bit of OCxM mask.
for correct operation there should be a shift by 3, cause bits 2:0 are in the low word and bit 3 is in the high word not bit 2.

spoken in code:

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#define STM32_TIM_CCMR1_OC1M(n)             ((((n) & 7) << 4) |             \
                                             (((n) >> 2) << 16))

should be

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#define STM32_TIM_CCMR1_OC1M(n)             ((((n) & 7) << 4) |             \
                                             (((n) >> 3) << 16))

The error exists for all OCxM Bit masks.

Greets

Tec

[tecnologic]

for Center aligned mode i added the following in line 593 of STM32 TIMv1 driver file pwm_lld.c:

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  /* Timer configured and started.*/
  pwmp->tim->CR1   = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS |
                     STM32_TIM_CR1_CEN | pwmp->config->cr1;

cr1 was as well declared in pwm_lld.h as element of PWMConfig structure.

as config you could use:

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              144000000UL,   // use PWM system clock
              (pwmcnt_t)(144000000UL/(u32Freq*2)),  //use double freq due to center aligned PWM
              NULL,
              {
               {PWM_OUTPUT_ACTIVE_HIGH | PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH, NULL},
               {PWM_OUTPUT_ACTIVE_HIGH | PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH, NULL},
               {PWM_OUTPUT_ACTIVE_HIGH | PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH, NULL},
               {PWM_OUTPUT_DISABLED, NULL}
              },
              STM32_TIM_CR1_CMS(1), //CR1
              0, //CR2
              0, //BDTR
              0 //DIER

Next i would give 3.0 a try.

[tecnologic]

Hi,

i just pulled the branch kernel_3_dev and brought my code to compile.
in chvt.h i had a problem with this line, gcc didnt like the cast.

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-    vtp->vt_next->vt_prev = (void *)&ch.vtlist;
+    vtp->vt_next->vt_prev = ch.vtlist.vt_next; //tecnologic

the ch.cpp ported to the new api i attached below.
in ch.hpp there were some type errors, i also attached my new file.

maybe this is helpfull

Greets

Tec