irq handler loop after reading a single byte via i2c

[mukululul]

Hi,
I am using i2c to access a SE95D, a MAX7111 and a PCA 9548A.
The Tempsensor and the DIO Mux work fine they both use 2 byte access.
The PCA9548A needs a one byte read this seems to cause a irq loop when calling the write one byte.
So the sequence is
i2cMasterReceiveTimeout(current_i2c_drv, deviceAdress, f_pCmd->data, 1,100);
i2cMasterTransmitTimeout(current_i2c_drv, deviceAdress, f_pCmd->data, 1, 0, 0, 100);

the transmit never returns and chibios locks up.

When I stop with the jtag debugger I can see that
static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp)
is called high frequently.
I get event=65 and regSR2 3 which seems to be a switch value which is not served.

This is the function:

Code: Select all

static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
  I2C_TypeDef *dp = i2cp->i2c;
  uint32_t regSR2 = dp->SR2;
  uint32_t event = dp->SR1;

  /* Interrupts are disabled just before dmaStreamEnable() because there
     is no need of interrupts until next transaction begin. All the work is
     done by the DMA.*/
  switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
  case I2C_EV5_MASTER_MODE_SELECT:
    if ((i2cp->addr >> 8) > 0) { 
      /* 10-bit address: 1 1 1 1 0 X X R/W */
      dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr);
    } else {
      dp->DR = i2cp->addr;
    }
    break;
  case I2C_EV9_MASTER_ADD10:
    /* Set second addr byte (10-bit addressing)*/
    dp->DR = (0xFF & (i2cp->addr >> 1));
    break;
  case I2C_EV6_MASTER_REC_MODE_SELECTED:
    dp->CR2 &= ~I2C_CR2_ITEVTEN;
    dmaStreamEnable(i2cp->dmarx);
    dp->CR2 |= I2C_CR2_LAST;                 /* Needed in receiver mode. */
    if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2)
      dp->CR1 &= ~I2C_CR1_ACK;
    break;
  case I2C_EV6_MASTER_TRA_MODE_SELECTED:
    dp->CR2 &= ~I2C_CR2_ITEVTEN;
    dmaStreamEnable(i2cp->dmatx);
    break;
  case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
    /* Catches BTF event after the end of transmission.*/
    if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) {
      /* Starts "read after write" operation, LSB = 1 -> receive.*/
      i2cp->addr |= 0x01;
      dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
      return;
    }
    dp->CR2 &= ~I2C_CR2_ITEVTEN;
    dp->CR1 |= I2C_CR1_STOP;
    wakeup_isr(i2cp, RDY_OK);
    break;
  default:
    break;
  }
  /* Clear ADDR flag. */
  if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
    (void)dp->SR2;
}

I find it strange that the default path is not doing anything.

Any ideas if this bug is already fixed?
I am using 2.6.1.

Thanks a lot for helping.

Rgards
Michael

[Giovanni]

There is a bug in the STM32F1 that prevents one byte receive operations with DMA. Are you using an F1?

Giovanni

[mukululul]

Hi Giovanni,
yes. It is a STM32F103CBT.

How can I get around it?

Thank you for your help.

Regards
Michael

[Giovanni]

You may read 2 bytes and ignore the second one. Reading one byte would require a new driver without DMA.

Giovanni

[mukululul]

Hi Giovanni,
thanks for the fast reply. I will try this. Is this bug also relevant for write?
Thanks
Michael

[Giovanni]

Just read. Newer STM32s are not affected.

Giovanni

[mukululul]

Hi Giovanni,
what exactly is newer?
Newer revision or different series like STM32F4xx?
I got revision Z.
I see that there are “Z”, “Y” or “1” or “2” or “X”.
Not sure if Z is the oldest or the newest.

Regards
Michael

[Giovanni]

The information is in the Errata document, Z and 1 are the latest.

Giovanni

[mukululul]

Hi Giovanni,
I dont wanna use to much of your time but in case you have some left for me I would appreciate some help identifing the which has this i2c DMA problem.
My Processor STM32F103RBT has a Revision 1 printed on the chip.
In the Datasheet it is mentioned that a register contains the revision, does chibios support a function which can read this register?
Can I access the register with jtag?

In your last answer you said that 1 and Z are the latest revisions, did I understand this correctly?

So my Processor is a Rev 1 and it shows the Problem. Did you expect this? I had the impression from your last answers that the later STM32F103 Revs do not have this i2c dma problem.

Maybe you can point me to the correct document where you found the information since I was not able to find it yet. I looked in CD00190234.pdf where they list the revisions but its not clear to me if the order they list it also means that the last the newest is.

For the circumvention, I am not sure if this is a solution for all devices which need single byte read since some may not tolerate a second byte if it supports only one.

Would be great if you could shed some light on this.

Thanks.
Michael

[Giovanni]

Probably I was not clear, my fault. All F1 devices are affected regardless they silicon version. By newer devices I meant newer families.

Giovanni