STM32F303 ADC

[Sync]

I am trying to implement a control loop using the F303s ADC sampling my signal and adjusting a PWM value accordingly.

To test the speed at which the conversions are occurring I made a simple callback that uses palTogglePad() to change the state of a pin.
This works fine, however I cannot seem to get a rate higher than 350kHz.

The sampling time is set to 1.5 clock cycles, so I should be faster than that.
I'm starting to suspect that there is an underlying clock problem, my mcuconf.h is as follows:

Code: Select all

#define STM32_NO_INIT                       FALSE
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0
#define STM32_HSI_ENABLED                   TRUE
#define STM32_LSI_ENABLED                   TRUE
#define STM32_HSE_ENABLED                   FALSE
#define STM32_LSE_ENABLED                   FALSE
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSI
#define STM32_PREDIV_VALUE                  1
#define STM32_PLLMUL_VALUE                  16
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV2
#define STM32_PPRE2                         STM32_PPRE2_DIV1
#define STM32_MCOSEL                        STM32_MCOSEL_SYSCLK
#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV1
#define STM32_ADC34PRES                     STM32_ADC34PRES_DIV1
#define STM32_USART1SW                      STM32_USART1SW_PCLK
#define STM32_USART2SW                      STM32_USART2SW_PCLK
#define STM32_USART3SW                      STM32_USART3SW_PCLK
#define STM32_UART4SW                       STM32_UART4SW_PCLK
#define STM32_UART5SW                       STM32_UART5SW_PCLK
#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK
#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK
#define STM32_TIM1SW                        STM32_TIM1SW_PCLK2
#define STM32_TIM8SW                        STM32_TIM8SW_PLLX2
#define STM32_RTCSEL                        STM32_RTCSEL_LSI
#define STM32_USB_CLOCK_REQUIRED            TRUE
#define STM32_USBPRE                        STM32_USBPRE_DIV1P5

/*
 * ADC driver system settings.
 */
#define STM32_ADC_USE_ADC1                  TRUE
#define STM32_ADC_USE_ADC3                  FALSE
#define STM32_ADC_ADC12_DMA_PRIORITY        2
#define STM32_ADC_ADC34_DMA_PRIORITY        2
#define STM32_ADC_ADC12_IRQ_PRIORITY        5
#define STM32_ADC_ADC34_IRQ_PRIORITY        5
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5
#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5
#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_DUAL_MODE                 FALSE

Interestingly I cannot see SYSCLK on the MCO pin, when I select PLLDIV2 I can see a nice 32MHz waveform. Am I missing something obvious or is there so much overhead that I cannot sample that fast with a callback? If so, how should I read the values?

[Giovanni]

Are you doing a single sample operation per call? it would kill the performance.

Try doing a large number of conversions with a single call, you should see much better results.

Giovanni

[Sync]

Yes, I'm reading the ADC four times and averaging the results.

I'm not sure if I can read larger chunks at one time because I have to react according to the values read back.

I'm rather confused why I cannot get SYSCLK to output something, I still suspect that I'm only running with 8MHz.
Increasing the number of samples results in slower frequencies on my pin. Calculating from there suggests that the ADC is sampling with 9MHz or slower...

Edit:
Adding one sample to the buffer adds about 105ns to the time before the pin toggles again. This suggests a frequency of 9.5MHz/1.5clock cycles = 6.3MHz for the clock... Plus or minus the overhead.

Edit2:
Changing ADC12PRES to 0 which should make the ADC use AHB as clock source changes nothing, which I think points further to some issue with the PLL...