STM32F30x ADC PLL clocks bug

[mobyfab]

Hi,

There is currently a bug in how the ADC clocks are enable when using the PLL clock source.

I had to manually write the RCC register to have it working, else it would just hang at the calibration.

Code: Select all

  RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12 | ~RCC_CFGR2_ADCPRE34; //erase register
  RCC->CFGR2 |= RCC_CFGR2_ADCPRE12_DIV128 | RCC_CFGR2_ADCPRE34_DIV32; // set precalers
  adcStart(&ADCD1, NULL);
  adcStart(&ADCD3, NULL);

From mcuconf.h

Code: Select all

...
#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV128
#define STM32_ADC34PRES                     STM32_ADC34PRES_DIV32
...
#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_ADCCK
#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_ADCCK
...

This does not occur when using the AHB clock source.

I have not looked into the source code yet, maybe the RCC code is simply missing?

This got me so crazy that I swapped a chip (This is for a custom board using an STM32F303RCT6)

[Giovanni]

Hi,

Thanks for finding, I will look into this before 2.6.5.

Giovanni

[mobyfab]

The code is present in os/hal/platforms/STM32F30x/hal_lld.c line 184.

Maybe the values needs to be cleared before applying, or only work with the PLL running first.

I will check in the reference manual.