[DONE][STM32F30x] 144MHz PWM

[tecnologic]

Hi All,

i finaly found the problem with setting the 144MHz Clock source for the advanced Timers.

Code: Select all

RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |
               STM32_USART2SW  | STM32_TIM8SW    | STM32_TIM1SW   |
               STM32_I2C2SW    | STM32_I2C1SW    | STM32_USART1SW;

#if STM32_ACTIVATE_PLL
  /* PLL activation.*/
  RCC->CR   |= RCC_CR_PLLON;
  while (!(RCC->CR & RCC_CR_PLLRDY))
    ;                                       /* Waits until PLL is stable.   */
#endif

As u can see the PLL is activated after the bits STM32_TIM1SW and STM32_TIM8SW were "set" but they are not set cause:

The bit is writable only when the following conditions occur: clock system = PLL, and AHB
and APB2 subsystem clock not divided respect the clock system.
The bit is reset by hardware when exiting from the previous condition (user must set the bit
again in case of a new switch is required)

So these bits could not be set before the pll is running. They stay 0. I only moved the set of RCC->CFGR3 to the end of the function.

hope this solves the problem with the hal finally .

Greetings

Tec

[Giovanni]

Hi,

Thanks for finding. I had to add some extra checks to hal_lld.h, could you give the fix a try? I have no F3 HW where I am.

Fixed as bug #525.

Giovanni

[tecnologic]

Hi Giovanni,

this was not the hole fix. The bits will only set when the clock source is switched to pll. please have look at these changes;
https://bitbucket.org/Tecnologic/chibio ... 2528821d30

Code: Select all

os/hal/ports/STM32/STM32F30x/hal_lld.c

                STM32_HPRE;

   RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;

 

+  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |

+               STM32_USART2SW  | STM32_I2C2SW    | STM32_I2C1SW   |

+               STM32_USART1SW;

+

 #if STM32_ACTIVATE_PLL

   /* PLL activation.*/

   RCC->CR   |= RCC_CR_PLLON;

     ;                                       /* Waits until PLL is stable.   */

 #endif

 

-  /* After PLL activation because the special requirements for TIM1 and

-     TIM8 bits.*/

-  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |

-               STM32_USART2SW  | STM32_TIM8SW    | STM32_TIM1SW   |

-               STM32_I2C2SW    | STM32_I2C1SW    | STM32_USART1SW;

-

   /* Flash setup and final clock selection.   */

   FLASH->ACR = STM32_FLASHBITS;

 

   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

     ;                                       /* Waits selection complete.    */

 #endif

+

+  /* After PLL activation because the special requirements for TIM1 and

+     TIM8 bits.*/

+  RCC->CFGR3 |= STM32_TIM8SW    | STM32_TIM1SW;

 #endif /* !STM32_NO_INIT */

 }

 

Änderungen nebeneinander Datei anzeigen
os/hal/ports/STM32/STM32F30x/hal_lld.h

 #elif STM32_TIM1SW == STM32_TIM1SW_PLLX2

 #if (STM32_SW != STM32_SW_PLL) ||                                           \

     (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \

-    (STM32_PPRE2 != STM32_PPRE2_DIV2)

+    (STM32_PPRE2 != STM32_PPRE2_DIV1)

 #error "double clock mode cannot be activated for TIM1 under the current settings"

 #endif

 #define STM32_TIM1CLK               (STM32_PLLCLKOUT * 2)

 #elif STM32_TIM8SW == STM32_TIM8SW_PLLX2

 #if (STM32_SW != STM32_SW_PLL) ||                                           \

     (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \

-    (STM32_PPRE2 != STM32_PPRE2_DIV2)

+    (STM32_PPRE2 != STM32_PPRE2_DIV1)

 #error "double clock mode cannot be activated for TIM8 under the current settings"

 #endif

 #define STM32_TIM8CLK               (STM32_PLLCLKOUT * 2)

With this changes the clock config will be set correctly, verified on my custom stm32f303RC Board and on the F3Discovery. Both work as expected.

Regards

Tec

[Giovanni]

Change committed, thanks.

Giovanni

[tecnologic]

Thanks, pulled the change.

Change tested and worked.

Regards

Tec