HSI trim deffines missing for F0

[rew]

The bootloader leaves HSITRIM set to the slowest trim value, while most code assumes the internal clock is trimmed about right. (within one percent as documented).
So.. now I have:

Code: Select all

  // Define is missing for F0. 
#ifndef RCC_CR_HSITRIM_4
#define RCC_CR_HSITRIM_4 0x80
#endif

  RCC->CR = (RCC->CR & ~RCC_CR_HSITRIM) |  RCC_CR_HSITRIM_4;

in my "main()'.

The easy fix would be to define the HSITRIM_4 bit just like the other families.

Or I might use:
( ( (RCC_CR_HSITRIM<<1)& ~ RCC_CR_HSITRIM) >> 1) // the highest bit of HSITRIM.

But I doubt that anybody (Including me in two weeks) reading that will understand.

[Giovanni]

I am not sure to understand the suggestion, the current code does not touch HSITRIM because it is meant to be a calibration value.

Giovanni

[rew]

HSITRIM is not the calibration value. The calibration value is stored outside of our reach. The trim value is added to the calibration value. The default trim value is 16 (from a 0-31 range) and the calibration value is factory adjusted to result in the 1% calibration of the internal RC clock.

The bootloader however has a bad bug that it tries to reset the TRIM value to the "DEFAULT" value. Someone at ST misread the datasheet and coded the trim value to be set to zero instead of the default value of "16", thus trimming the internal RC for the slowest possible setting instead of the center, calibrated value.

The bootloader bug is of no concern in many cases. If you boot-load, and then reset the chip, the hardware reset will load the correct value again. Only if you tell the bootloader to jump to your application do you hit this problem.

But ChibiOS could even without this bug define the HSITRIM bits for stm32f0xx processors as it does for all the other stm32fYxx processor families (Y != 0).