STM32F746 DISCO Bss Section Overflow

[lemmy]

DTCM RAM ("ram3" 64k) doesn't seem large enough to hold the main stack, process stack, BSS, NOCACHE and ETH once a project starts to

Which of these groups could be reassigned to "ram0"?

[Giovanni]

You can move anything in ram0 but then you have to handle cache coherency by yourself, see this article: http://chibios.org/dokuwiki/doku.php?id ... _dma_guide

Moving stacks should not be an issue unless you have DMA buffers as automatic variables.

Only the Ethernet driver strictly requires non-cached buffers because it is DMA-intensive.

Giovanni

[lemmy]

Thank you Giovanni,

ITCM-RAM "ram4" is the 16KB area optimized for DMA accesses that could be used for dedicated DMA RAM?

[Giovanni]

ITCM RAM is for code only, DMAs don't have accesses to it. DTCM can be accessed by DMAs.

Giovanni

[lemmy]

Ah I see, thank you. Should then your article http://chibios.org/dokuwiki/doku.php?id=chibios:articles:cortexm7_dma_guide say :-

Advantages

Does not require active runtime-handling.
It is perfectly transparent to the application.
Does not have any performance hit.
DTCM RAM is already non cached and can be used for DMA buffers.
The STM32F7xx has a 64KB area optimized for DMA accesses that could be used for this.

[Giovanni]

Nope, that would be RAM2 (there are two normal RAM banks as slaves), it is 16k and it is not the DTCM.

You need to use the MPU to make RAM2 non-cacheable, there is an option in the HAL settings for that.

Giovanni

[lemmy]

Thank you Giovanni