Hi barthess,
I studied the problem some more and my conclusions are:
1) The PWR->PVD should be left enabled. Safety considerations are true but the RM specifies that it must stay enabled if the RTC is clocked by HSE. I don't want to have two different behaviors depending on the selected clock source so better keep it enabled like you did.
2) Waiting for write completion is only required for PRL, CNT, ALR registers, the CR register is not part of the backup domain and can always be written.
3) Waiting for APB1 synchronization is only required for DIV, CNT, ALR registers, the CR register is not part of the backup domain and can always be read.
I modified the driver according to this and also made some minor optimizations, can you review it when you have some time? the driver looks thin now, I like it (and I will like it even more after confirmation it works

).
The RTCv2 driver will have to wait after 2.4.0, after the RTCv1 driver is OK I will freeze this version.
Giovanni