ChibiOS/RT 3.1.3 + STM32F756 + IAR

[cipher]

Hi Everyone
Im currently evaluating Chibios/RT for use on our custom hardware running STM32F756ZGT chip.
I managed to create an IAR project with IAR 7.60.1 by referencing the example project for the STM32F7-DISCO board.
I did get the LwIP and web server running, tried the I2C driver and everything seemed to be fine, however i have discovered that i definitely have a problem with the IAR linker file the way it is setup right now.
I tried to play with SPI driver and this is when the issues started to show up i guess

When i was setting up the project, i was referencing the original gnu ld files and trying to recreate the memory layout in IAR linker file.
however, i can see that the __heap_base__ and __heap_end__ symbols are not being properly exported to the OS.

I also got some ideas from the STM32F303 demo, the only one that has the IAR project but the STM32F7 chip memory layout is way more complicated than the F303.

I attach my IAR linker file here

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\linker\ST\IcfEditor\stm32f7xx.xml" */
/*
 * ST32F746xG Ethernet setup.
 * 
 * RAM1 - Data, Heap.
 * RAM2 - ETH.
 * RAM3 - Main Stack, Process Stack, BSS, NOCACHE.
 *
 * Notes:
 * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
 */
 
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00200000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ITCMF_start__ = 0x00200000;
define symbol __ICFEDIT_region_ITCMF_end__   = 0x002FFFFF;
define symbol __ICFEDIT_region_AXIF_start__  = 0x08000000;
define symbol __ICFEDIT_region_AXIF_end__    = 0x080FFFFF;
define symbol __ICFEDIT_region_ITCMR_start__ = 0x00000000; /* ITCM-RAM START */
define symbol __ICFEDIT_region_ITCMR_end__   = 0x00003FFF; /* ITCM-RAM END */
define symbol __ICFEDIT_region_DTCMR_start__ = 0x20000000; /* DTCM-RAM START */
define symbol __ICFEDIT_region_DTCMR_end__   = 0x2000FFFF; /* DTCM-RAM END */
define symbol __ICFEDIT_region_SRAM1_start__ = 0x20010000; /* SRAM1 START */
define symbol __ICFEDIT_region_SRAM1_end__   = 0x2004BFFF; /* SRAM1 END */
define symbol __ICFEDIT_region_SRAM2_start__ = 0x2004C000; /* SRAM2 START */
define symbol __ICFEDIT_region_SRAM2_end__   = 0x2004FFFF; /* SRAM2 END */
define symbol __ICFEDIT_region_BKPR_start__  = 0x40024000; /* BCKP SRAM START */
define symbol __ICFEDIT_region_BKPR_end__    = 0x40024FFF; /* BCKP SRAM END */

/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__   = 0x400;
/**** End of ICF editor section. ###ICF###*/

/* Size of the IRQ Stack (Main Stack).*/
define symbol __ICFEDIT_size_irqstack__   = 0x400;

define memory mem with size = 4G;
define region ITCMF_region  =   mem:[from __ICFEDIT_region_ITCMF_start__ to __ICFEDIT_region_ITCMF_end__];
define region AXIF_region   =   mem:[from __ICFEDIT_region_AXIF_start__  to __ICFEDIT_region_AXIF_end__ ];
define region ITCMR_region  =   mem:[from __ICFEDIT_region_ITCMR_start__ to __ICFEDIT_region_ITCMR_end__];
define region DTCMR_region  =   mem:[from __ICFEDIT_region_DTCMR_start__ to __ICFEDIT_region_DTCMR_end__];
define region SRAM_region   =   mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__] 
                              | mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
define region SRAM1_region  =   mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__];
define region SRAM2_region  =   mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
define region BKPR_region   =   mem:[from __ICFEDIT_region_BKPR_start__  to __ICFEDIT_region_BKPR_end__ ];

define symbol __heap_base__    = __ICFEDIT_region_SRAM1_start__;
define symbol __heap_end__     = __ICFEDIT_region_SRAM1_end__;
define symbol __ICFEDIT_size_sysheap__ = 0x5000;

define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   {section CSTACK};
define block IRQSTACK  with alignment = 8, size = __ICFEDIT_size_irqstack__ {};
define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     {};
define block SYSHEAP   with alignment = 8  {section SYSHEAP};
define block DATABSS   with alignment = 8 {section __nocache_base__, zeroinit};

initialize by copy { readwrite };
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
do not initialize  { section .noinit };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ITCMF_region  { readonly };
place in ITCMR_region  { section .textrw };
place in DTCMR_region  { first block IRQSTACK, block CSTACK, block DATABSS };
place in SRAM1_region  { first section SYSHEAP, block HEAP, readwrite };
place in SRAM2_region  { section __eth_base__ };
place in BKPR_region   { section .backup_sram };

I would really appreciate any help in getting me going under IAR with proper linker file that would have basically the same settings as the ld gnu linker file in the original F7DISCO demo.

I tried to search this forum and the __heap_base__ symbols problem is explained for KEIL compilers but i couldn't find anything in regards to IAR

Thanks in advance

[Giovanni]

Hi,

I am not very expert of the IAR linker files so I don't know if it is possible to replicate the whole GNU structure as-is.

Note that you can avoid those symbols entirely, just specify a value for CH_CFG_MEMCORE_SIZE to the desired heap size and the symbols will no more be required.

Giovanni

[cipher]

Hi Giovanni
Yes i tried to do this, but there is another issue, is i specify the number of bytes for the heap, the heap will be placed into the DTCM region, and i want to put it in to the regular RAM1 cached region, since i need the DTCM ram for other things.
What would be the non-intrusive way to place the heap in the SRAM1?

Thank you

[Giovanni]

Hi,

Then you need to create those symbols... it is very linker-specific, maybe you should seek support in the IAR forums, I don't know it in sufficient detail.

Giovanni

[Al B]

Hi Cipher,

I am also working on using Chibios with IAR, but not on F7 series.

If you look at the core_init routine that uses the CH_CFG_MEMCORE_SIZE = 0 parameter, it uses a static buffer.
IAR likely takes this memory off the stack, which would mean CSTACK, which the .icf specifies as DTCMR.
Further, CSTACK in your .icf is only 0x400, which would be way too small for most dynamic allocations. As you are likely taking a large memory chuck, it has likely blown right through that stack. You could just edit the __ICFEDIT_size_cstack__ var and set to 0x8000 or so (need to check .map to ensure enough room left for the .data and .bss sections).

I think core_init() might also need some further consideration about memory usage, but its probably fine for tiny allocations.

So you really need to get the __heap_base__ and __heap_end__ working and placed where you want them (SRAM1), which can be tricky with IAR linker/assembler.
I notice in the .icf that __ICFEDIT_size_sysheap__ = 0x5000 is defined, but not used. However your__heap_base__ and __heap_end__ defines should work fine. And FYI, I don't think that HEAP (not SYSHEAP) block is used, it seems to be there because ST's .icf files had it, whereas ChibiOS is using the SYSHEAP.

Check the .map file and make sure that all of the SYSHEAP$$Base, SYSHEAP$$Base __heap_base__ and __heap_end__ are all correct. While at it you should also check all the other $$Base and $$Limit entries and make sure they are OK too.

Another place to check is the cstartup.s file and do global search on the "__heap" uses, to make sure that the definitions that you provide from the .icf file, aren't being overridden. There are some tricks that are used to try to get the correct __heap_base__ and __heap_end__ values in the code that I've seen. Since F7 has so many memory blocks, those tricks aren't needed and should be removed. (Again, FYI I notice that SYSHEAP and HEAP assignment order have been switched in the icf place in assignment and some of this tricky code might cause your sysheap to "disappear"

If you also include the cstartup.s (or whatever has the _iar_program_start and the PSP setting), I might be able to comment further.
Once I figure out how/where to submit code, I'll try to put up a working IAR example.

Hopefully this helps,
Al

[cipher]

Hi Al
Thank you for the information
So, here is what puzzles me, When i enable the

Code: Select all

define exported symbol __heap_base__    = __ICFEDIT_region_SRAM1_start__;
define exported symbol __heap_end__     = __ICFEDIT_region_SRAM1_end__;

in the .icf file, i get the following linking error:

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Error[Li006]: duplicate definitions for "__heap_end__"; in "command line/config", and ".......\Obj\cstartup.o" 
Error[Li006]: duplicate definitions for "__heap_base__"; in "command line/config", and ".......\Obj\cstartup.o" 

Here is the cstartup.c file that is included with chibios for cortex m7

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/*
    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

/**
 * @file    ARMCMx/IAR/cstartup.s
 * @brief   Generic IAR Cortex-Mx startup file.
 *
 * @addtogroup ARMCMx_IAR_STARTUP
 * @{
 */

#if !defined(__DOXYGEN__)

        MODULE  ?cstartup

CONTROL_MODE_PRIVILEGED SET 0
CONTROL_MODE_UNPRIVILEGED SET 1
CONTROL_USE_MSP SET 0
CONTROL_USE_PSP SET 2

        AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
        PRESERVE8

        SECTION .intvec:CODE:NOROOT(3)

        SECTION CSTACK:DATA:NOROOT(3)
        PUBLIC  __main_thread_stack_base__
__main_thread_stack_base__:
        PUBLIC  __heap_end__
__heap_end__:

        SECTION SYSHEAP:DATA:NOROOT(3)
        PUBLIC  __heap_base__
__heap_base__:

        PUBLIC  __iar_program_start
        EXTERN  __vector_table
        EXTWEAK __iar_init_core
        EXTWEAK __iar_init_vfp
        EXTERN  __cmain

        SECTION .text:CODE:REORDER(2)
        REQUIRE __vector_table
        THUMB
__iar_program_start:
        cpsid   i
        ldr     r0, =SFE(CSTACK)
        msr     PSP, r0
        movs    r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
        msr     CONTROL, r0
        isb
        bl      __early_init
        bl      __iar_init_core
        bl      __iar_init_vfp
        b       __cmain

        SECTION .text:CODE:NOROOT:REORDER(2)
        PUBWEAK __early_init
__early_init:
        bx      lr

        END

#endif /* !defined(__DOXYGEN__) */

/**< @} */

And here is my updated .icf file

Code: Select all

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\linker\ST\IcfEditor\stm32f7xx.xml" */
/*
 * ST32F746xG Ethernet setup.
 * 
 * RAM1 - Data, Heap.
 * RAM2 - ETH.
 * RAM3 - Main Stack, Process Stack, BSS, NOCACHE.
 *
 * Notes:
 * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
 */
 
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00200000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ITCMF_start__ = 0x00200000;
define symbol __ICFEDIT_region_ITCMF_end__   = 0x002FFFFF;
define symbol __ICFEDIT_region_AXIF_start__  = 0x08000000;
define symbol __ICFEDIT_region_AXIF_end__    = 0x080FFFFF;
define symbol __ICFEDIT_region_ITCMR_start__ = 0x00000000; /* ITCM-RAM START */
define symbol __ICFEDIT_region_ITCMR_end__   = 0x00003FFF; /* ITCM-RAM END */
define symbol __ICFEDIT_region_DTCMR_start__ = 0x20000000; /* DTCM-RAM START */
define symbol __ICFEDIT_region_DTCMR_end__   = 0x2000FFFF; /* DTCM-RAM END */
define symbol __ICFEDIT_region_SRAM1_start__ = 0x20010000; /* SRAM1 START */
define symbol __ICFEDIT_region_SRAM1_end__   = 0x2004BFFF; /* SRAM1 END */
define symbol __ICFEDIT_region_SRAM2_start__ = 0x2004C000; /* SRAM2 START */
define symbol __ICFEDIT_region_SRAM2_end__   = 0x2004FFFF; /* SRAM2 END */
define symbol __ICFEDIT_region_BKPR_start__  = 0x40024000; /* BCKP SRAM START */
define symbol __ICFEDIT_region_BKPR_end__    = 0x40024FFF; /* BCKP SRAM END */

/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/

/* Size of the IRQ Stack (Main Stack).*/
define symbol __ICFEDIT_size_irqstack__   = 0x400;

define memory mem with size = 4G;
define region ITCMF_region  =   mem:[from __ICFEDIT_region_ITCMF_start__ to __ICFEDIT_region_ITCMF_end__];
define region AXIF_region   =   mem:[from __ICFEDIT_region_AXIF_start__  to __ICFEDIT_region_AXIF_end__ ];
define region ITCMR_region  =   mem:[from __ICFEDIT_region_ITCMR_start__ to __ICFEDIT_region_ITCMR_end__];
define region DTCMR_region  =   mem:[from __ICFEDIT_region_DTCMR_start__ to __ICFEDIT_region_DTCMR_end__];
define region SRAM_region   =   mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__] 
                              | mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
define region SRAM1_region  =   mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__];
define region SRAM2_region  =   mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
define region BKPR_region   =   mem:[from __ICFEDIT_region_BKPR_start__  to __ICFEDIT_region_BKPR_end__ ];


define exported symbol __heap_base__    = __ICFEDIT_region_SRAM1_start__;
define exported symbol __heap_end__     = __ICFEDIT_region_SRAM1_end__;


define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   {section CSTACK};
define block IRQSTACK  with alignment = 8, size = __ICFEDIT_size_irqstack__ {};
define block SYSHEAP   with alignment = 8 {section SYSHEAP};
define block DATABSS   with alignment = 8 {section __nocache_base__, zeroinit};

initialize by copy { readwrite };
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
do not initialize  { section .noinit };
do not initialize  { section SYSHEAP };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ITCMF_region  { readonly };
place in ITCMR_region  { section .textrw };
place in DTCMR_region  { first block IRQSTACK,  block DATABSS, section NO_CACHE };
place in SRAM1_region  { first block CSTACK, readwrite,  readwrite object memp.o, section SRAM1, last block SYSHEAP };
place in SRAM2_region  { section SRAM2 };
place in BKPR_region   { section .backup_sram };

I removed the HEAP define since its not used

Im still trying to figure this one out, so if you have any suggestions i would really appreciate it

Thank you

[Al B]

Hi Cipher,

Yes they would be duplicate because they have to be defined in cstartup.s to properly work for other STM processors that don't have some many memory regions.

I posted a fully working IAR project with associated cstartup.c code here:
viewtopic.php?f=24&t=3360 Re: CORTEX_VTOR_INIT

You should be able to reuse a lot of that if, and make memory changes for your processor get added into that icf file. There is also a readme file in the IAR folder that may be of assistance.

However to save you time, took a stab at the icf, and tried to attach but this editor is complaining about invalid message for some reason. Maybe to do with the code insert boxes you used. By the way, how do you get those boxes?

So sorry about this, but I am have to insert the code text, which you will have to paste back into icf file, and clean up the formatting again, as well as finish it off. It compiles, but I can't test it as no F7.

========F756.icf starts here:===============
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\linker\ST\IcfEditor\stm32f7xx.xml" */
/*
* ST32F746xG Ethernet setup.
*
* ??? Not sure what these chucks are referring to
* RAM1 - Data, Heap.
* RAM2 - ETH.
* RAM3 - Main Stack, Process Stack, BSS, NOCACHE.
*
* Suggestions on memory layout:
* ITCMF: NVIC, ROM
* SRAM1: HEAP, SYSHEAP
* DTCM-RAM: DATABSS
* SRAM2: IRQSTACK, CSTACK
*
* Questions:
* - Not sure if there are Eth chunks that need to be separately placed, and not sure if they are best placed in a specific RAM section for perf reasons?
* - why did you "do not initialize SYSHEAP" ?
* - what is the __nocache_base__ section?
* - what is readwrite object memp.o?
* - what is section NO_CACHE?
* - with the placements below, see if .textrw is properly placed, and if not then will need to be placed
* General comment:
* - I personally find that it might have been easier if name like __ICFEDIT_region_ROM1_start__ ROM1, RAM1, RAM2, RAM3, RAM4... where defined and then comments as the the specific name/size beside them
* Notes:
* BSS is placed in DTCM RAM in order to simplify DMA buffers management.
*/

/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00200000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ITCMF_start__ = 0x00200000;
define symbol __ICFEDIT_region_ITCMF_end__ = 0x002FFFFF; /* ROM 1M */
define symbol __ICFEDIT_region_AXIF_start__ = 0x08000000;
define symbol __ICFEDIT_region_AXIF_end__ = 0x080FFFFF; /* ROM2 1M */
define symbol __ICFEDIT_region_ITCMR_start__ = 0x00000000; /* ITCM-RAM START */
define symbol __ICFEDIT_region_ITCMR_end__ = 0x00003FFF; /* ITCM-RAM END */
define symbol __ICFEDIT_region_DTCMR_start__ = 0x20000000; /* DTCM-RAM START */
define symbol __ICFEDIT_region_DTCMR_end__ = 0x2000FFFF; /* DTCM-RAM END */
define symbol __ICFEDIT_region_SRAM1_start__ = 0x20010000; /* SRAM1 START */
define symbol __ICFEDIT_region_SRAM1_end__ = 0x2004BFFF; /* SRAM1 END */
define symbol __ICFEDIT_region_SRAM2_start__ = 0x2004C000; /* SRAM2 START */
define symbol __ICFEDIT_region_SRAM2_end__ = 0x2004FFFF; /* SRAM2 END */
define symbol __ICFEDIT_region_BKPR_start__ = 0x40024000; /* BCKP SRAM START */
define symbol __ICFEDIT_region_BKPR_end__ = 0x40024FFF; /* BCKP SRAM END */

/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x3000; /* Size of the process stack */
define symbol __ICFEDIT_size_heap__ = 0x100; /* Used to mark heap (heap + sysheap) maximum size limit */

/**** End of ICF editor section. ###ICF###*/

/* Size of the IRQ Stack (Main Stack).*/
define symbol __ICFEDIT_size_irqstack__ = 0x400;

define memory mem with size = 4G;
define region ITCMF_region = mem:[from __ICFEDIT_region_ITCMF_start__ to __ICFEDIT_region_ITCMF_end__];
define region AXIF_region = mem:[from __ICFEDIT_region_AXIF_start__ to __ICFEDIT_region_AXIF_end__ ];
define region ITCMR_region = mem:[from __ICFEDIT_region_ITCMR_start__ to __ICFEDIT_region_ITCMR_end__];
define region DTCMR_region = mem:[from __ICFEDIT_region_DTCMR_start__ to __ICFEDIT_region_DTCMR_end__];
define region SRAM1_region = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__];
define region SRAM2_region = mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
define region BKPR_region = mem:[from __ICFEDIT_region_BKPR_start__ to __ICFEDIT_region_BKPR_end__ ];

define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__, fixed order { };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__, fixed order {section CSTACK};
define block DATABSS with alignment = 8, fixed order {readwrite, zeroinit};
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__, fixed order {section HEAP};
define block SYSHEAP with alignment = 8 {section SYSHEAP};

initialize by copy {readwrite};
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
do not initialize {section .noinit};

keep { section .intvec };

place at address mem:__ICFEDIT_intvec_start__ {readonly section .intvec};

place in ITCMF_region {readonly}; /* ROM Region */

place at start of SRAM2_region {block IRQSTACK}; /* IRQ stack */
place in SRAM2_region {block CSTACK}; /* Process stack */
place in DTCMR_region {block DATABSS}; /* Textdata region */
place in SRAM1_region {block HEAP}; /* Sys Heap size limit marker */
place at end of SRAM1_region {block SYSHEAP}; /* Sys Heap available for allocations */
place in BKPR_region {section .backup_sram };


/* Define stack and memory addresses for kernel usage */
define exported symbol __main_stack_base__ = __ICFEDIT_region_SRAM2_start__;
define exported symbol __main_stack_end__ = __main_stack_base__ + __ICFEDIT_size_irqstack__; /* Note: End refers to empty stack */
define exported symbol __process_stack_base__ = __main_stack_end__;
define exported symbol __main_thread_stack_base__ = __process_stack_base__; /* Note: Main thread uses process stack */
define exported symbol __process_stack_end__ = __process_stack_base__ + __ICFEDIT_size_cstack__;



/* these are the parts that I had questions about above
define block DATABSS with alignment = 8 {section __nocache_base__, zeroinit};

do not initialize { section SYSHEAP };

place in ITCMR_region { section .textrw };
place in DTCMR_region { first block IRQSTACK, block DATABSS, section NO_CACHE };
place in SRAM1_region { first block CSTACK, readwrite, readwrite object memp.o, section SRAM1, last block SYSHEAP };
*/
===========F756.icf ends here================

Once you clean it up and make changes based on the questions in the file, I could review it if you like.

Thanks,
Al

[Al B]

Hi Cipher,

On retrospect, some further thoughts on this:
1) I have not looked at this chip in detail, but it is likely that the different memories have special attributes, and as such it is very likely that the my suggested section placements will need improvement. I was only considering trying to get the code to work, not to optimized its performance. For example, the ITCM being 16k is quite likely special, the 2 flash/rom sections might have different performance and there may be differences between DTCM and the larger RAM sections??? Thus the default section placements could likely use some improvement.
2) I suggest that you look VERY closely at ST's most basic version of .icf's as well as their associated startup code for this processors or a similar one, since if there are special initialization requirements and section placement requirements, they should likely be covered by them (the experts). I don't have access to these. There may be some code needed to be added to the cstartup.s to support the F7/F756?
2b) And related to this, my general comment below about naming of __ICFEDIT_region_ROM1_start__ etc. Please ignore that. You should be using the naming that has been generated by ICF editor tool, and adjust the .icf code after that section to match it and add meaningful descriptions about it.
3) You are going to have to go through the .map file and verify (by inspecting the map address placements as well as using the debugger to verify the __iar_init... zero/copy memory initializations done properly and do testing to verify the mainline LED blinky and an ISR work properly and have proper stack placements).
4) If you are trying to do optimizations by specific code section placements (I suggest you do this as a subsequent step, if at all), then you will have to know more on how to use IAR C compiler output section placement, and update .icf linker file and possibly assembler code AND be able to use map files and debugger to verify all the sections are properly placed and initialized (which you likely will by the time you are finished step 3

Good luck,
Al