I'm making a board.h file for the F429ZI Nucleo-144. It's been going pretty well. When I'm done, and have some basic webserver working, I want to submit it to the offical repo in an effort to contribute, since I saw the Nucleo 144s are not officially in the examples repo.
I'm using Win7 and KEIL 5.16a, and the project builds alright, though I've noticed some warnings that appear as I change the default PAL configuration.
I started my board.h editing task by changing the #def names to match the pin functions that are on the board (mainly ETH and USB OTG). I did this by modifying a board header for the F429 Discovery. It was after I changed the pin names that I noticed some of these compiler warnings about:
os\hal\boards\ST_NUCLEO_F429ZI\board.c(28): warning: #61-D: integer operation result is out of range
Which takes me to
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const PALConfig pal_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
Previously, I was able to prevent this warning from appearing by resetting all the arguments from
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PIN_AFIO_AF(GPIOA_UART_TX, 7)
to
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PIN_AFIO_AF(GPIOA_UART_TX, 0)
for all of VAL_GPIOA_AFRL and VAL_GPIOA_AFRH
So at one point, I was able to clear these warnings by setting all pin AF functionality for the F429 Discovery to default 0.
Now, as I've finished naming all the pins, and am actually setting MODER, OTYPER, to match what the pin type needs, I've managed to avoid seeing many of these warnings as I change back to the actual functionality I need for the Nucleo, for USB and ETH.
But now I've finished the AF configuration, and still need to finish MODER, OTYPE configs. But I don't want to move on until I get this resolved.
Here is my GPIOA setup:
Names are complete
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/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_ETH_RMII_REF_CLK 1U
#define GPIOA_ETH_RMII_MDIO 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_ETH_RMII_CRS_DV 7U
#define GPIOA_PIN8 8U
#define GPIOA_OTG_FS_VBUS 9U
#define GPIOA_OTG_FS_ID 10U
#define GPIOA_OTG_FS_DM 11U
#define GPIOA_OTG_FS_DP 12U
#define GPIOA_SWDIO 13U
#define GPIOA_SWCLK 14U
#define GPIOA_PIN15 15U
I/O assignment is not complete yet.
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/*
* IO lines assignments.
*/
#define LINE_BUTTON PAL_LINE(GPIOA, 0U)
#define LINE_ETH_RMII_REF_CLK PAL_LINE(GPIOA, 1U)
#define LINE_MEMS_INT2 PAL_LINE(GPIOA, 2U)
#define LINE_LCD_B5 PAL_LINE(GPIOA, 3U)
#define LINE_LCD_VSYNC PAL_LINE(GPIOA, 4U)
#define LINE_LCD_G2 PAL_LINE(GPIOA, 6U)
#define LINE_ACP_RST PAL_LINE(GPIOA, 7U)
#define LINE_I2C3_SCL PAL_LINE(GPIOA, 8U)
#define LINE_UART_TX PAL_LINE(GPIOA, 9U)
#define LINE_UART_RX PAL_LINE(GPIOA, 10U)
#define LINE_LCD_R4 PAL_LINE(GPIOA, 11U)
#define LINE_LCD_R5 PAL_LINE(GPIOA, 12U)
#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
#define LINE_TP_INT PAL_LINE(GPIOA, 15U)
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/*
* GPIOA setup:
*
* PA0 - PIN0 (input pullup)
* PA1 - ETH_RMII_REF_CLK (input pullup)
* PA2 - ETH_RMII_MDIO (input pullup)
* PA3 - PIN3 (input pullup)
* PA4 - PIN4 (input pullup)
* PA5 - PIN5 (input pullup)
* PA6 - PIN6 (input pullup)
* PA7 - ETH_RMII_CRS_DV (input pullup)
* PA8 - PIN8 (input pullup)
* PA9 - OTG_FS_VBUS (input pullup)
* PA10 - OTG_FS_ID (input pullup)
* PA11 - GPIOA_OTG_FS_DM (input pullup)
* PA12 - GPIOA_OTG_FS_DP (input pullup)
* PA13 - SWDIO (input pullup)
* PA14 - SWCLK (input pullup)
* PA15 - PIN15 (input pullup)
*/
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
PIN_MODE_INPUT(GPIOA_ETH_RMII_REF_CLK) | \
PIN_MODE_INPUT(GPIOA_ETH_RMII_MDIO) | \
PIN_MODE_INPUT(GPIOA_PIN3) | \
PIN_MODE_INPUT(GPIOA_PIN4) | \
PIN_MODE_INPUT(GPIOA_PIN5) | \
PIN_MODE_INPUT(GPIOA_PIN6) | \
PIN_MODE_INPUT(GPIOA_ETH_RMII_CRS_DV) | \
PIN_MODE_INPUT(GPIOA_PIN8) | \
PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \
PIN_MODE_INPUT(GPIOA_OTG_FS_ID) | \
PIN_MODE_INPUT(GPIOA_OTG_FS_DM) | \
PIN_MODE_INPUT(GPIOA_OTG_FS_DP) | \
PIN_MODE_INPUT(GPIOA_SWDIO) | \
PIN_MODE_INPUT(GPIOA_SWCLK) | \
PIN_MODE_INPUT(GPIOA_PIN15))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_REF_CLK) | \
PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDIO) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) | \
PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \
PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \
PIN_OSPEED_HIGH(GPIOA_ETH_RMII_REF_CLK) | \
PIN_OSPEED_HIGH(GPIOA_ETH_RMII_MDIO) | \
PIN_OSPEED_HIGH(GPIOA_PIN3) | \
PIN_OSPEED_HIGH(GPIOA_PIN4) | \
PIN_OSPEED_HIGH(GPIOA_PIN5) | \
PIN_OSPEED_HIGH(GPIOA_PIN6) | \
PIN_OSPEED_HIGH(GPIOA_ETH_RMII_CRS_DV) | \
PIN_OSPEED_HIGH(GPIOA_PIN8) | \
PIN_OSPEED_HIGH(GPIOA_OTG_FS_VBUS) | \
PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | \
PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \
PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \
PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
PIN_OSPEED_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
PIN_PUPDR_PULLUP(GPIOA_ETH_RMII_REF_CLK) | \
PIN_PUPDR_PULLUP(GPIOA_ETH_RMII_MDIO) | \
PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
PIN_PUPDR_PULLUP(GPIOA_ETH_RMII_CRS_DV) | \
PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
PIN_PUPDR_PULLUP(GPIOA_OTG_FS_VBUS) | \
PIN_PUPDR_PULLUP(GPIOA_OTG_FS_ID) | \
PIN_PUPDR_PULLUP(GPIOA_OTG_FS_DM) | \
PIN_PUPDR_PULLUP(GPIOA_OTG_FS_DP) | \
PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
PIN_PUPDR_PULLUP(GPIOA_SWCLK) | \
PIN_PUPDR_PULLUP(GPIOA_PIN15))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
PIN_ODR_HIGH(GPIOA_ETH_RMII_REF_CLK) | \
PIN_ODR_HIGH(GPIOA_ETH_RMII_MDIO) | \
PIN_ODR_HIGH(GPIOA_PIN3) | \
PIN_ODR_HIGH(GPIOA_PIN4) | \
PIN_ODR_HIGH(GPIOA_PIN5) | \
PIN_ODR_HIGH(GPIOA_PIN6) | \
PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \
PIN_ODR_HIGH(GPIOA_PIN8) | \
PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \
PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \
PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
PIN_ODR_HIGH(GPIOA_SWDIO) | \
PIN_ODR_HIGH(GPIOA_SWCLK) | \
PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | \
PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) | \
PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \
PIN_AFIO_AF(GPIOA_PIN3, 0) | \
PIN_AFIO_AF(GPIOA_PIN4, 0) | \
PIN_AFIO_AF(GPIOA_PIN5, 0) | \
PIN_AFIO_AF(GPIOA_PIN6, 0) | \
PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \
PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
PIN_AFIO_AF(GPIOA_PIN15, 0))
Reg macros (unmodified from original, they look correct to me)
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/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
#define PIN_ODR_LOW(n) (0U << (n))
#define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
I can't figure out which of these macros is evaluating to be out of range, since the compiler takes me to where these setting are all OR'ed together into a PAL config type (as shown at the very top as the first code snippet). This means it might just be one of these things which are evaluating to some kind of overflowed number. Which one might it be? Is there a better way for me to approach solving this one?
