ADCv2 Topic is solved

[neums]

Hi,
short question to ADCv2 (adc_lld_start_conversion):
Why writing ADC_CR2_CONT two times? And why not writing ADC_CR2_SWSTART?

Code: Select all

  /* The start method is different dependign if HW or SW triggered, the
     start is performed using the method specified in the CR2 configuration.*/
  if ((cr2 & ADC_CR2_SWSTART) != 0) {
    /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
    adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;

    /* Finally enabling ADC_CR2_SWSTART.*/
    adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
  }

Thanks

[Giovanni]

Hi,

We need to enforce ADC_CR2_CONT even if not specified in the structure.

ADC_CR2_SWSTART is optionally written in the configuration structure but only in case of SW triggering, it must not be specified for HW triggering.

Comments could be better there.

Giovanni

[neums]

Hi,
but in the code the ADC_CR2_SWSTART flag is reset in CR2. And ADC_CR2_CONT is written twice.

[Giovanni]

ADC_CR2_CONT is not written twice, it is kept to 1 during the two writes like all bits specified in cr2. I want only ADC_CR2_SWSTART to toggle, if specified.

Giovanni

[neums]

Sure...
2nd question: How to configure software triggered discontinuous mode when the ADC_CR2_CONT is forced? In the STM32F4 reference manual is described that a single sequence conversion is done with ADC_CR2_CONT=0.
Why it has to be enforced?

[Giovanni]

There is an assumption in the driver for the ADC to be in continuous mode. All channels in a conversion group are meant to be converted together.

The ADC driver implements a generic ADC behavior, it does not necessarily support all features of the underlying HW. The discontinuous mode is very STM32-specific.

Giovanni

[neums]

Hi,
how to use the EOC and JEOC interrupt? I just see the DMA full transfer isr.

[neums]

Hi,
in the adc_lld_start_conversion the value L in sqr1 is not set. This value defines the length of the conversion group:

Code: Select all

  /* ADC setup.*/
  adcp->adc->SR    = 0;
  adcp->adc->SMPR1 = grpp->smpr1;
  adcp->adc->SMPR2 = grpp->smpr2;
  adcp->adc->SQR1  = grpp->sqr1;
  adcp->adc->SQR2  = grpp->sqr2;
  adcp->adc->SQR3  = grpp->sqr3;

In the ADCv3 this value is set with the high level part value num_channels:

Code: Select all

  adcp->adcm->SMPR1 = grpp->smpr[0];
  adcp->adcm->SMPR2 = grpp->smpr[1];
  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
  adcp->adcm->SQR2  = grpp->sqr[1];
  adcp->adcm->SQR3  = grpp->sqr[2];
  adcp->adcm->SQR4  = grpp->sqr[3];

My channels are not converted if L is not set to num_channels. I tested it with the debugger. When I set L to num_channels then the ADC converts all channels defined in the sqr registers. Is this a bug or am i doing somthing wrong?

[Giovanni]

Hi,

I can't see any reason for the driver to NOT do that, it is a bug. Opening a ticket.

About EOC, there is no need for that, the DMA interrupt is sufficient, JEOC is not used because injected conversions are not supported by the driver model, a low level API could be implemented for that.

Giovanni

[neums]

Hi,
thanks for opening a ticket.
To your 2nd answer. The interrupt is available for the error callback (ADC_SR_OVR leads to the same interrupt vector as ADC_SR_EOC and ADC_SR_JEOC). Could it be possible to have an event callback in the ADC driver for EOC and JEOC which is called in OSAL_IRQ_HANDLER(STM32_ADC_HANDLER) if it is unequal NULL? The event callback whould be local user code whos responsible to dispatch the ISR reason exactly. That might be plattform independent and a STM user has the opportunity the implement an EOC or JEOC callback. Sure, JEOC is only avaible if the injected channels whould be introduced in the low level part of this certain ADC driver. But this is also plattform independent.

Usecase:
I want to convert 10 channels continuously and SW triggered by interrupt. But i need also a timer triggered channel with higher priority.

Thanks