1) You'll get a 10kHz noise coming from the motor.
2) VESC is able to do the sampling in the right moments. It also uses chibios, so... take a look at the source code.
3) The ADC is not infinitely fast. It takes some time to gather the samples. Are you using all three ADCs? The 'F405 has three ADCs. (Giovanni seems to "know" that you're using an F405. I don't see that mentioned in your post. Ah! wait! In the subject ok!)
4) Can you limit "max/min PWM" to say 40% around the midpoint? (that might be a bit much, but the results might shed light on the issue). If the problem then goes away, the cases where you see "differing signal levels" are when the PWM is close to one of the endpoints and the actual ADC sample is happening after the signal has switched again already.
Synchronization ADC and center-aligned PWM STM32F405
Moderator: RoccoMarco
Re: Synchronization ADC and center-aligned PWM STM32F405
Regarding the 10kHz noise, SVM and center-aligned PWM give the best tradeoff and I have to stick to that for this project. Measurements are taken from a gate driver and have some filtering before reaching the ADC.
I know about VESC. Actually what I am developing is inspired by it, but with modifications so I can implement my own control algorithms. I have posted questions in their forum too. I have been through most of the code, specially the control and the configuration, but that did not solve any of my doubts.
I have not tried yet to trigger all 3 ADCs simultaneously, but I will give it a try next day. Anyhow, the test I did in one channel with the injected conversion was failing to sample at the right moment, so this will probably go the same way.
From my tests, with some of the channels being around 90% duty cycle it failed to capture them in the same state. I will investigate lower duty cycles when I go back to the lab and check if there's a threshold there for the triggering, although having to go lower than 90% can be a big loss of capabilities.
Thanks!!
I know about VESC. Actually what I am developing is inspired by it, but with modifications so I can implement my own control algorithms. I have posted questions in their forum too. I have been through most of the code, specially the control and the configuration, but that did not solve any of my doubts.
I have not tried yet to trigger all 3 ADCs simultaneously, but I will give it a try next day. Anyhow, the test I did in one channel with the injected conversion was failing to sample at the right moment, so this will probably go the same way.
From my tests, with some of the channels being around 90% duty cycle it failed to capture them in the same state. I will investigate lower duty cycles when I go back to the lab and check if there's a threshold there for the triggering, although having to go lower than 90% can be a big loss of capabilities.
Thanks!!
Re: Synchronization ADC and center-aligned PWM STM32F405
Again, my suggestion of lowering the "max PWM" is to try to measure WHEN the sampling happens. If you find it only goes wrong above 87% PWM, then you know the sampling is happening say 6.5% into the 50 microsecond PWM period. Then I hope that this 3.25 microseconds can be traced to "something" say the sampling delay, or the time it takes to take two samples.
The way I understand it you trigger three conversion using "injection" at the moment the timer is at the "midpoint". Now the ADC might need to finish the current conversion, then switch to the channel you requested and then it needs to do two conversions before it gets to the last channel. So... you have about 3 conversion times that need to take place before the last sample is taken. Check your ADC config Is it running at the max possible speed? Isn't the ADC run off a 14MHz clock with around 14-16 clocks per conversion? That's awfully close to the 3.25 microseconds calculated from my example 87%....
The way I understand it you trigger three conversion using "injection" at the moment the timer is at the "midpoint". Now the ADC might need to finish the current conversion, then switch to the channel you requested and then it needs to do two conversions before it gets to the last channel. So... you have about 3 conversion times that need to take place before the last sample is taken. Check your ADC config Is it running at the max possible speed? Isn't the ADC run off a 14MHz clock with around 14-16 clocks per conversion? That's awfully close to the 3.25 microseconds calculated from my example 87%....
Re: Synchronization ADC and center-aligned PWM STM32F405
Thanks!
Using 1 injected channel per ADC (and not triggering regular channels) seems to work OK from 1% to 99% duty cycle of the three PWM signals. Curiously, setting PWM signals with 50% duty cycle sometimes yielded sketchy results in the ADC...
As a random fact, half-full FIFO interrupts were happening at almost 70kHz.
I tried to move on to other parts of the firmware to clear my thoughts for a bit.
Using 1 injected channel per ADC (and not triggering regular channels) seems to work OK from 1% to 99% duty cycle of the three PWM signals. Curiously, setting PWM signals with 50% duty cycle sometimes yielded sketchy results in the ADC...
As a random fact, half-full FIFO interrupts were happening at almost 70kHz.
I tried to move on to other parts of the firmware to clear my thoughts for a bit.