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uint32_t ccr = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) |
STM32_MDMA_CCR_CTCIE | /* On transfer complete.*/
STM32_MDMA_CCR_TCIE; /* On transfer error. */
It should be
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STM32_MDMA_CCR_TEIECode: Select all
STM32_MDMA_CCR_TCIESecondly, the driver uses MDMA_REQUEST_QUADSPI_TC signal to MDMA for sending the data, which I think is not correct. In the datasheet section 23.3.12 it says
so when the send is entered with this condition the transfer would never take place. I believe MDMA_REQUEST_QUADSPI_FIFO_TH is the correct signal, and I tested it to fix the hang while sending where the above mentioned condition is met.In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is
triggered by a write in the FIFO through QUADSPI_DR.
So, at this stage the Data out is working as intended, double checked on Logic Analyser. Now I am stuck at the issue of receiving the data. I can clearly see the instruction being sent on the bus without issue, and the chip responds as expected, and I can see the bytes appearing in the DR register of QSPI and also FLEVEL value being set correctly to show bytes have successfully been received by QSPI peripheral and retained in FIFO. But from here on forth, the copy by MDMA from DR to memory does not take place.I can see the CNBTR value decreasing to 0 from previous set transaction size, but the bytes in the memory are not even being overwritten with some value, tested by setting the buffer with fill value before hand and checking after the transaction is over. I also observed that at the end of the MDMA transaction completion the QSPI has its DR FIFO flushed as well. I can confirm that the memory is located in AXI SRAM (0x24000000) as required, and have tried with both MDMA_REQUEST_QUADSPI_FIFO_TH and MDMA_REQUEST_QUADSPI_TC signals resulting in similar behaviour. Any direction from here onwards to debug the issue will be greatly appreciated.
