21.6.x branch, L422 RCC issue Topic is solved

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tzarc
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21.6.x branch, L422 RCC issue

Post by tzarc »

Branch: ChibiOS 21.6.x stable
Compiler: arm-none-eabi-gcc 8.3.1
Platform/board: custom STM32L422KB, adapted from ST_NUCLEO32_L432KC
Failure: build errors --

Code: Select all

./lib/chibios/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc: In function 'pll_init':
./lib/chibios/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc:179:44: error: 'RCC_PLLCFGR_PLLP_Pos' undeclared (first use in this function); did you mean 'RCC_PLLCFGR_PLLN_Pos'?
 #define STM32_PLLP                  (0U << RCC_PLLCFGR_PLLP_Pos)
                                            ^~~~~~~~~~~~~~~~~~~~
./lib/chibios/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc:343:34: note: in expansion of macro 'STM32_PLLP'
                  STM32_PLLQEN  | STM32_PLLP   |
                                  ^~~~~~~~~~
./lib/chibios/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc:179:44: note: each undeclared identifier is reported only once for each function it appears in
 #define STM32_PLLP                  (0U << RCC_PLLCFGR_PLLP_Pos)
                                            ^~~~~~~~~~~~~~~~~~~~
./lib/chibios/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc:343:34: note: in expansion of macro 'STM32_PLLP'
                  STM32_PLLQEN  | STM32_PLLP   |
                                  ^~~~~~~~~~


Was attempting to build against L422KB (well, L412KB but close enough), but can't do so as it seems as if it's configured incorrectly in the stm32_registry.h.

There is no PLLP on the chip (when looking at STM32CubeMX), though the stm32_registry.h says so.

I had to make two changes to get things to compile:
  • Setting STM32_RCC_PLL_HAS_P to FALSE
  • Seemingly changing STM32_PLLPEN to STM32_PLLPDIV, as the former was already defined in hal_lld.h.

I'm not sure if the second is correct -- PLLQ/PLLR etc. also look like they have the same issue with STM32_PLLPEN/STM32_PLLPDIV.

Code: Select all

diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
index 2b3af669d5..9d649d288f 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
@@ -222,7 +222,7 @@

 #else /* !STM32_RCC_PLL_HAS_P */
 #define STM32_PLLP                  0U
-#define STM32_PLLPEN                0U
+#define STM32_PLLPDIV               0U
 #endif /* !STM32_RCC_PLL_HAS_P */

 /*---------------------------------------------------------------------------*/
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
index ecb2efc5de..8fcb5dba41 100644
--- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
@@ -353,7 +353,7 @@
 #define STM32_RCC_HAS_HSE                   TRUE

 #define STM32_RCC_HAS_PLL                   TRUE
-#define STM32_RCC_PLL_HAS_P                 TRUE
+#define STM32_RCC_PLL_HAS_P                 FALSE
 #define STM32_RCC_PLL_HAS_Q                 TRUE
 #define STM32_RCC_PLL_HAS_R                 TRUE
tzarc
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Re: 21.6.x branch, L422 RCC issue

Post by tzarc »

Also noticed one other thing -- all L4xx boards have GPIOH as well. The L422 doesn't currently have it enabled in stm32_registry.h, and likely needs to be enabled in other MCUs as well as the L422.

EDIT: Looks like GPIOD, too.
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Giovanni
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Re: 21.6.x branch, L422 RCC issue

Post by Giovanni »

Hi,

Fixed as #1198.

Note, not fixed in 21.6.x branch because it will be recreated starting from trunk before next release.

Giovanni
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Re: 21.6.x branch, L422 RCC issue

Post by JSStabl »

Fix #1198 breaks compilation for all STM496 (and maybe even L4A6) with less than 169 pins, since they don't have a GPIOI.

Example Chip is the STM32L496Vx Series.

Is there an elegant way to fix this? Our workaround is to revert this commit (sorry I can't navigate sourceforge that well):

https://github.com/ChibiOS/ChibiOS/comm ... 616ee9458a
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Giovanni
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Re: 21.6.x branch, L422 RCC issue

Post by Giovanni »

JSStabl wrote:Fix #1198 breaks compilation for all STM496 (and maybe even L4A6) with less than 169 pins, since they don't have a GPIOI.

Example Chip is the STM32L496Vx Series.

Is there an elegant way to fix this? Our workaround is to revert this commit (sorry I can't navigate sourceforge that well):

https://github.com/ChibiOS/ChibiOS/comm ... 616ee9458a


Hi,

In which version? do you mind opening another topic? this one is about 21.6.x which is closed.

Giovanni
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