STM32 SPIv2 v2 driver reset Topic is solved

[fvantienen]

For the STM32F7 I noticed that the v2 driver didn't function properly, when the lld_disable was called from the lld_start and the state was not SPI_STOP. This is because both CR1 and CR2 are fully reset, which somehow leads to wrong clock pulses being send.

In order to fix this only the SPE should be reset (os/hal/ports/STM32/LLD/SPIv2/hal_spi_v2_lld.c):

Code: Select all

static void spi_lld_disable(SPIDriver *spip) {
.....
-    /* Clearing SPE and the rest.*/
-    spip->spi->CR1 = 0U;
-    spip->spi->CR2 = 0U;
.....
+    /* Clearing SPE */
+    spip->spi->CR1 &= ~SPI_CR1_SPE;
.....

[Giovanni]

Hi,

Could you post a code example where this behavior is triggered? repeated spiStart()?

If possible post also your SPI configuration structure.

You fix is clear, is the root cause that is not clear. Perhaps the driver should implement the whole (overly complicated) SPI disable procedure described in the reference manual.

Code: Select all

1. Wait until FTLVL[1:0] = 00 (no more data to transmit).
2. Wait until BSY=0 (the last data frame is processed).
3. Disable the SPI (SPE=0).
4. Read data until FRLVL[1:0] = 00 (read all the received data).

Even with your fix, only steps 2 and 3 are implemented. I think steps 1 and 4 are not necessary because DMA TX is over and DMA RX has already counted the expected number of RX frames.

Giovanni

[Giovanni]

Committed a change, closing.

Giovanni