STM32H743 QSPI in SPI mode

[dflogeras]

STM32H743ZI on ChibiOS-21.11.4

I have a QSPI flash chip (S24FL128LAGMFM) wired to the micro with all four data lines, plus clock and nCS.

I've never used the QSPI driver yet, so I'm attempting just to read the chip ID. I have started the QSPI with:

Code: Select all

  static const WSPIConfig WSPIcfg1 = {
    .end_cb           = 0x0,
    .error_cb         = qspi_error,
    .dcr              = STM32_DCR_FSIZE(24U) |        /* 16MB device.         */
                        STM32_DCR_CSHT(7U)            /* cycles delay +1.  */
  };
  wspiStart( &WSPID1, &WSPIcfg1 );
  

And then I read the chip ID with:

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#define DATA  0x01000100
#define RDID 0x9F
    wspi_command_t cmd = {
      .cfg = DATA,
      .cmd = RDID,
      .addr = 0,
      .alt = 0,
      .dummy = 0,
    };

    uint8_t buf[3];
    wspiReceive( &WSPID1, &cmd, sizeof( buf ), &buf[0] );

I can see on my logic analyzer that the hardware has successfully clocked out the 0x9F command on MOSI, and then reads back 3 bytes on MISO (that match the device datasheet).

However, after that point I'm stuck here:

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#0  0x08005024 in chSysHalt (reason=0x80169d8 "MDMA failure")
    at ../os/rt/src/chsys.c:229
#1  0x0800418c in osalSysHalt (reason=0x80169d8 "MDMA failure")
    at ../os/hal/osal/rt-nil/osal.h:544
#2  0x080042ba in wspi_lld_serve_mdma_interrupt (wspip=0x24000198 <WSPID1>,
    flags=13107201) at ../os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c:87
#3  0x08003e3a in mdma_serve_interrupt (mdmachp=0x240000d8 <mdma+4>)
    at ../os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.c:75
#4  0x08003e60 in Vector228 ()
    at ../os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.c:93
#5  <signal handler called>

Specifically, it seems the error hook was called because the STM32_MDMA_CISR_TEIF flag is set. Also the CESR register is concatenated with those flags, and it seems to have contained 0xc8. I am not sure how to decode that, or what I am doing wrong here.

Hopefully something stupid.

[Giovanni]

Hi,

The reasons for TEIF are in the RM:

The transfer error interrupt flag (TEIF) is set when:
•A bus error occurs during a MDMA read or a write access
•The address alignment does not correspond to the data size
•The block size is not a multiple of the data size (for source and/or destination): this
error is activated on the last transfer and the error address points to the last transfer
(which cannot be done)

Not sure what could cause that, look at your destination buffer position in memory.

Giovanni

[dflogeras]

Aha, yes it seems the MDMA did not like that buffer being in DTCM-RAM (0x20000000). I had it on my stack, but moving it to static global (which put it in AXI-RAM (0x24000000) got me past that.

I keep forgetting how complicated these devices can be.

Thank you very much for the pointer(s).
Dave