Another stm32h7 dual mode ADC bug Topic is solved

[mck1117]

In os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c, if you have dual mode ADC1/2 enabled, and also ADC3 enabled, the code starting on line 807 (adcp->adcm->CFGR2 = grpp->cfgr2; etc) stomps over the master ADC configuration set in lines 765-780. It's missing an else case there and just runs unconditionally, instead of only running on single ADCs. Fixing that makes dual mode ADC work properly!

example of the fix to cherry pick: https://github.com/FOME-Tech/ChibiOS/co ... cfaa8f0c5e

[Giovanni]

Hi,

Could you try this patch?

Code: Select all

Index: hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
===================================================================
--- hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c   (revision 17611)
+++ hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c   (working copy)
@@ -752,9 +752,9 @@
     adcp->adcs->ISR   = adcp->adcs->ISR;
     /* If a callback is set enable the overflow and analog watch dog interrupts. */
     if (grpp->error_cb != NULL) {
-    adcp->adcs->IER   = ADC_IER_OVRIE | ADC_IER_AWD1IE |
-                                        ADC_IER_AWD2IE |
-                                        ADC_IER_AWD3IE;
+      adcp->adcs->IER   = ADC_IER_OVRIE | ADC_IER_AWD1IE |
+                                          ADC_IER_AWD2IE |
+                                          ADC_IER_AWD3IE;
     }
     /* Configuring the CCR register with the user-specified settings
       in the conversion group configuration structure, static settings are
@@ -798,12 +798,9 @@
     /* ADC configuration.*/
     adcp->adcm->CFGR  = cfgr;
     adcp->adcs->CFGR  = cfgr;
-}
-#endif /* STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE */
-
-#if STM32_ADC_DUAL_MODE == FALSE || STM32_ADC_USE_ADC3 == TRUE
-  /* Configuration for ADC3 and single mode ADC1 */
-
+  } else {
+#if STM32_ADC_USE_ADC3 == TRUE
+    /* Configuration for ADC3 (skip ADCD1 in dual mode). */
     adcp->adcm->CFGR2   = grpp->cfgr2;
     adcp->adcm->PCSEL   = grpp->pcsel;
     adcp->adcm->LTR1    = grpp->ltr1;
@@ -824,7 +821,30 @@
     /* ADC configuration.*/
     adcp->adcm->CFGR  = cfgr;
 #endif
+  }
+#else
+  /* Configuration for ADC3 and single mode ADC1 */
+  adcp->adcm->CFGR2   = grpp->cfgr2;
+  adcp->adcm->PCSEL   = grpp->pcsel;
+  adcp->adcm->LTR1    = grpp->ltr1;
+  adcp->adcm->HTR1    = grpp->htr1;
+  adcp->adcm->LTR2    = grpp->ltr2;
+  adcp->adcm->HTR2    = grpp->htr2;
+  adcp->adcm->LTR3    = grpp->ltr3;
+  adcp->adcm->HTR3    = grpp->htr3;
+  adcp->adcm->AWD2CR  = grpp->awd2cr;
+  adcp->adcm->AWD3CR  = grpp->awd3cr;
+  adcp->adcm->SMPR1   = grpp->smpr[0];
+  adcp->adcm->SMPR2   = grpp->smpr[1];
+  adcp->adcm->SQR1    = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
+  adcp->adcm->SQR2    = grpp->sqr[1];
+  adcp->adcm->SQR3    = grpp->sqr[2];
+  adcp->adcm->SQR4    = grpp->sqr[3];
 
+  /* ADC configuration.*/
+  adcp->adcm->CFGR  = cfgr;
+#endif /* STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE */
+
   /* Starting conversion.*/
   adcp->adcm->CR   |= ADC_CR_ADSTART;
 }

Giovanni

[Giovanni]

Hi,

I committed this fix, could you give confirmation it is working for you?

Giovanni

[Giovanni]

Closing unconfirmed.

Giovanni