I've started a hazard3_dev branch for a RP2350 Hazard3 port. Its a functional POC at this point which supports SMP and has performance in line with, or slightly better than, the RP2350 ARM port in trunk. There are likely defects and I'm continuing to debug and test as I iterate on the POC.
Key things to discuss, what level of instruction set hell of RISCV do we want to embrace? Currently the code is split between Hazard3 specific code and RISCV-Common. The RISCV common code assumes RV32I and Zifencei although I've attempted to keep it RV64 clean.
riscv.h this is, effectively, a compatibility layer. However this is a common pattern in RISCV and likely not super controversial.
Feel free to poke around and any feedback or comments are greatly appreciated. The other controversial bit, which I will post more about later, is the interrupt code.
RP2350 Hazard3 (RISCV) Port
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