Now, a different project means looking at the (quite) different H7 flash. My brief looking at the H742/3/53 group that my chip is within, yields:
- These devices are all dual bank.
- There doesn't seem to be an analog of running in single bank mode, like in the F7 series.
- The registers in the FLASH peripheral that concern erasing and programming are all split into two (one for each bank).
The other approach would be to hide the two banks behind the API, and make it so that the driver figured out which registers to use, based on what sector an operation was performing on.
Any thoughts?
Has anyone took a stab at any of these more complex devices yet?