ChibiOS Free Embedded RTOS

Posted: **Mon Apr 29, 2019 8:07 pm**

Just FYI:

If I'd write such a bootloader, I'd link the bootloader to <top-of-flash>. When bootloading, the bootloader will write all application bytes, except for the vectors at 0x08000000 (8 bytes). Those need to be stored somewhere else. Downloading the bootloader to the chip is now a bit more difficult: you have to flash the first 8 bytes and the bootloader at the end. But now writing and linking an actual application program is like running on bare hardware: no changing of normal ld files etc.

Oh, and another thing: To jump to the application, with the CPU as much as possible in "reset condition" is difficult. I't think it is doable with the RCC, but if you get stuck, consider the following: To get the CPU in pristine state, set the watchdog timer to go off "soon". Store a "magic word" in ram somehwhere, and when the bootloader "boots", it checks that word before doing anything else. If it sees the magic, disable the watchdog, remove the magic, and jump to the application. Now you've had a hardware reset that should have done "everything right".

Putting the CPU back in "pristine state" is difficult. For example, ST gets it wrong in the ROM bootloader (at least for the STM32F072). When you ask the bootloader to "jump to application" your application will find the internal RC trimmed at -8% (about 7.36 MHz). They set the RC trim register to zero while the five bit reset-default is 0x10 (halfway between 0x00 and the max 0x1f). Async serial connection become "flaky" at -8% trim......

Posted: **Fri Jul 05, 2019 7:59 pm**

Sorry for the delay, I will post it on Monday.

Posted: **Tue Jul 09, 2019 9:09 am**

This is currently the linker file. I am also using SDRAM, so you may ignore the related parts.

Basically, only flash0 and flash1 are changed for moving the application data in flash and reserving 0x20000 of space for the bootloader.

Code: Select all

/*
    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

/*
 * ST32F746xG Ethernet setup.
 * 
 * RAM1 - Data, Heap.
 * RAM7 - ETH.
 * RAM3 - Main Stack, Process Stack, BSS, NOCACHE. 
 *
 * Notes:
 * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
 */
MEMORY
{
    flash0  : org = 0x08020000, len = 1M - 0x20000       /* Flash as AXIM (writable) */
    flash1  : org = 0x00220000, len = 1M - 0x20000       /* Flash as ITCM */
    flash2  : org = 0x00000000, len = 0
    flash3  : org = 0x00000000, len = 0
    flash4  : org = 0x00000000, len = 0
    flash5  : org = 0x00000000, len = 0
    flash6  : org = 0x00000000, len = 0
    flash7  : org = 0x00000000, len = 0
    ram0    : org = 0x20030000, len = 128k      /* SRAM1 + SRAM2 */
    ram1    : org = 0x20030000, len = 112k      /* SRAM1 */
    ram2    : org = 0x2004C000, len = 16k       /* SRAM2 */
    ram3    : org = 0x20000000, len = 64k       /* DTCM-RAM */
    ram5    : org = 0x40024000, len = 4k        /* BCKP SRAM */
    ram6    : org = 0x20010000, len = 128k      /* Reserved sampling RAM */
    ram7    : org = 0xC0000000, len = 16M       /* SDRAM space for user 
    memory */
    ram4    : org = 0xC1000000, len = 16M       /* SDRAM space Ethernet */
}

/* For each data/text section two region are defined, a virtual region
   and a load region (_LMA suffix).*/

/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash1);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);

/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash1);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);

/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash1);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);

/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);

/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash1);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);

/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);

/* RAM region to be used for Main stack. This stack accommodates the processing
   of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram3);

/* RAM region to be used for the process stack. This is the stack used by
   the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram3);

/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);

/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram3);

/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);

/* Stack rules inclusion.*/
INCLUDE rules_stacks.ld

/*===========================================================================*/
/* Custom sections for STM32F7xx.                                            */
/*===========================================================================*/

/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram3);

/* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram3);

SECTIONS
{
    /* Special section for non cache-able areas.*/
    .nocache (NOLOAD) : ALIGN(4)
    {
        __nocache_base__ = .;
        *(.nocache)
        *(.nocache.*)
        *(.bss.__nocache_*)
        . = ALIGN(4);
        __nocache_end__ = .;
    } > NOCACHE_RAM

    /* Special section for Ethernet DMA non cache-able areas.*/
    .eth (NOLOAD) : ALIGN(4)
    {
        __eth_base__ = .;
        *(.eth)
        *(.eth.*)
        *(.bss.__eth_*)
        . = ALIGN(4);
        __eth_end__ = .;
    } > ETH_RAM
}

/* Code rules inclusion.*/
INCLUDE rules_code.ld

/* Data rules inclusion.*/
INCLUDE rules_data.ld

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