ChibiOS Free Embedded RTOS

Posted: **Tue May 22, 2018 8:30 am**

Hi Giovanni,
Attached is a spreadsheet of the MCUs falling under the F4 & F2 HAL.
As it turns out there are a number of MCUs that actually belong in the "hal_lld_type2.h" based on their TIMPRE configuration.

Adapting the existing split header setup could be done by:
1. reworking the MCU assignments between "hal_lld_type1.h" and "hal_lld_type2.h" (per spreadsheet)
2. customise the STM32_TIMCLK1/2 setting code and move it from "hal_lld.h" into each of "hal_lld_type1.h" and "hal_lld_type2.h"

Do you think this is a good approach?

FYI I found a corruption in the F4 stm32_registry.h.
Just a bad character inserted somehow.

--

Bob

Code: Select all

Index: stm32_registry.h
===================================================================
--- stm32_registry.h   (revision 12042)
+++ stm32_registry.h   (working copy)
@@ -92,7 +92,7 @@
 /* Clock tree attributes.*/
 #define STM32_HAS_RCC_PLLSAI                TRUE
 #define STM32_HAS_RCC_PLLI2S                TRUE
-#define STM32_HAS_RCC_DCKCFGR               TRU§E
+#define STM32_HAS_RCC_DCKCFGR               TRUE
 #define STM32_HAS_RCC_DCKCFGR2              FALSE
 #define STM32_HAS_RCC_I2SSRC                TRUE
 #define STM32_HAS_RCC_I2SPLLSRC             FALSE

Posted: **Tue May 22, 2018 9:39 am**

Note that type1 and type2 is not just TIMPRE, there is a mess with I2S-related settings and register fields overlapping, reassigning... not sure if it is a good idea. F413 is the real oddball there.

Let's just add conditionals for the TIMPRE part in hal_lld.h.

Giovanni

Posted: **Wed May 23, 2018 6:44 am**

Does this meet the brief?

Code: Select all

Index: hal_lld.h
===================================================================
--- hal_lld.h   (revision 12042)
+++ hal_lld.h   (working copy)
@@ -221,8 +221,8 @@
 #else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
 #if (STM32_PPRE1 == STM32_PPRE1_DIV1) ||                                    \
     (STM32_PPRE1 == STM32_PPRE1_DIV2) ||                                    \
-    (STM32_PPRE1 == STM32_PPRE1_DIV4) ||                                    \
-    defined(__DOXYGEN__)
+    (STM32_PPRE1 == STM32_PPRE1_DIV4) && (STM32_TIMPRE_PRESCALE4 == TRUE)   \
+                                      || defined(__DOXYGEN__)
 #define STM32_TIMCLK1               STM32_HCLK
 #else
 #define STM32_TIMCLK1               (STM32_PCLK1 * 4)
@@ -230,8 +230,8 @@
 
 #if (STM32_PPRE2 == STM32_PPRE2_DIV1) ||                                    \
     (STM32_PPRE2 == STM32_PPRE2_DIV2) ||                                    \
-    (STM32_PPRE2 == STM32_PPRE2_DIV4) ||                                    \
-    defined(__DOXYGEN__)
+    (STM32_PPRE1 == STM32_PPRE1_DIV4) && (STM32_TIMPRE_PRESCALE4 == TRUE)   \
+                                      || defined(__DOXYGEN__)
 #define STM32_TIMCLK2               STM32_HCLK
 #else
 #define STM32_TIMCLK2               (STM32_PCLK2 * 4)
Index: hal_lld_type1.h
===================================================================
--- hal_lld_type1.h   (revision 12042)
+++ hal_lld_type1.h   (working copy)
@@ -1927,6 +1927,17 @@
  */
 #define STM32_PLLSAI_R_CLKOUT       (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
 
+/**
+ * @brief   TIMPRE multiply threshold flag.
+ * @note    When TIMPRE is set timer HCLK * 4 starts after prescaler 4.
+ */
+#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411x)     \
+                         || defined(STM32F412xx)
+#define STM32_TIMPRE_PRESCALE4      TRUE
+#else
+#define STM32_TIMPRE_PRESCALE4      FALSE
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
Index: hal_lld_type2.h
===================================================================
--- hal_lld_type2.h   (revision 12042)
+++ hal_lld_type2.h   (working copy)
@@ -1175,6 +1175,17 @@
  */
 #define STM32_ACTIVATE_PLLSAI       FALSE
 
+/**
+ * @brief   TIMPRE multiply threshold flag.
+ * @note    When TIMPRE is set timer HCLK * 4 starts after prescaler 4.
+ */
+#if defined(STM32F413xx)
+#define STM32_TIMPRE_PRESCALE4      FALSE
+#else
+#define STM32_TIMPRE_PRESCALE4      TRUE
+#endif
+
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
Index: stm32_registry.h
===================================================================
--- stm32_registry.h   (revision 12042)
+++ stm32_registry.h   (working copy)
@@ -92,7 +92,7 @@
 /* Clock tree attributes.*/
 #define STM32_HAS_RCC_PLLSAI                TRUE
 #define STM32_HAS_RCC_PLLI2S                TRUE
-#define STM32_HAS_RCC_DCKCFGR               TRU§E
+#define STM32_HAS_RCC_DCKCFGR               TRUE
 #define STM32_HAS_RCC_DCKCFGR2              FALSE
 #define STM32_HAS_RCC_I2SSRC                TRUE
 #define STM32_HAS_RCC_I2SPLLSRC             FALSE

Posted: **Sun May 27, 2018 11:38 am**

Hi,

I committed the patch but moved the STM32_TIMPRE_PRESCALE4 definition in the registry, this way it will be evident when adding new devices.

Giovanni

ChibiOS Free Embedded RTOS

Support for RCC_DKCFGR.TIMPRE in newer STM32

Re: Support for RCC_DKCFGR.TIMPRE in newer STM32

Re: Support for RCC_DKCFGR.TIMPRE in newer STM32

Re: Support for RCC_DKCFGR.TIMPRE in newer STM32

Re: Support for RCC_DKCFGR.TIMPRE in newer STM32