Excessive clock speed in predefined board
Posted: Sat Mar 30, 2013 11:46 am
Hi all,
So I will soon be working on a custom board that has an STM32F405. So in order to prepare my work I just started building the board directory with the board.c and board.h files. To begin with, I copied those from the classic ST_STM32F4_DISCOVERY board. As I first compiled the (pretty much empty) project, ChibiOS told me there was an #error : "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)". Now I saw those values and how the clock speed got defined in the os/hal/platforms/STM32F4xx/hal_lld.h, but I don't know what to change : is it the maximum speed that's wrong, or is it the defined speed ? I suppose I can go check out the manuals and datasheets for the STM32F405 just to see what values should be there, but if you already know of this problem, then great - and I thought I'd let you know, because it seems to come from one of Chibi's predefined boards, so any user will have this problem.
Cheers,
Charles
EDIT : Here's what I understood. Specifically, it's the APB1 frequency (STM32_PCLK1) Chibi is not happy with. In the ST_STM32F4_DISCOVERY board all that's defined is STM32_HSE (value : 8 MHz), which is then transmitted with a certain prescaler to STM32_SYSCLK which is then transmitted with a certain prescaler to STM32_HCLK which is then transmitted with a certain prescaler to STM32_PCLK1 - that's how it should happen right ? And when you look at the figures (STM32_PCLK1_MAX is 42 MHz when STM32F4XX is defined), you realize even if you don't divide HSE at all it's still clearly small enough.
EDIT EDIT : Actually, there's more to it. By default, STM32_SYSCLK receives STM32_PLLCLKOUT rather than directly STM32_HSECLK. STM32_PLLCLKOUT is calculated from PLL characteristics and STM32_PLLCLKIN, which itself comes from STM32_HSECLK. I still don't see how it managed to be too big. Help !
So I will soon be working on a custom board that has an STM32F405. So in order to prepare my work I just started building the board directory with the board.c and board.h files. To begin with, I copied those from the classic ST_STM32F4_DISCOVERY board. As I first compiled the (pretty much empty) project, ChibiOS told me there was an #error : "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)". Now I saw those values and how the clock speed got defined in the os/hal/platforms/STM32F4xx/hal_lld.h, but I don't know what to change : is it the maximum speed that's wrong, or is it the defined speed ? I suppose I can go check out the manuals and datasheets for the STM32F405 just to see what values should be there, but if you already know of this problem, then great - and I thought I'd let you know, because it seems to come from one of Chibi's predefined boards, so any user will have this problem.
Cheers,
Charles
EDIT : Here's what I understood. Specifically, it's the APB1 frequency (STM32_PCLK1) Chibi is not happy with. In the ST_STM32F4_DISCOVERY board all that's defined is STM32_HSE (value : 8 MHz), which is then transmitted with a certain prescaler to STM32_SYSCLK which is then transmitted with a certain prescaler to STM32_HCLK which is then transmitted with a certain prescaler to STM32_PCLK1 - that's how it should happen right ? And when you look at the figures (STM32_PCLK1_MAX is 42 MHz when STM32F4XX is defined), you realize even if you don't divide HSE at all it's still clearly small enough.
EDIT EDIT : Actually, there's more to it. By default, STM32_SYSCLK receives STM32_PLLCLKOUT rather than directly STM32_HSECLK. STM32_PLLCLKOUT is calculated from PLL characteristics and STM32_PLLCLKIN, which itself comes from STM32_HSECLK. I still don't see how it managed to be too big. Help !